4 Asymmetrical Footprint

Removal of input capacitors strictly on one side of the butterfly pinout provides flexibility to users who desire a cost-effective, one-sided input path. Some select system designs can require a VIN entry point exclusively through a single end of the package containing the majority of the capacitors, rather than a double-sided VIN package with capacitors on each end. Although removing a number of input capacitors on a single side allows for design flexibility, it also carries trade-offs in terms of SW-node ringing. Generally, greater SW-node ringing is present when a single VIN rail is used and a number of input capacitors are removed from one side of the package. One can balance the need for reducing SW-node noise and reducing design cost by removing the suggested amount of capacitors. If users choose to proceed with this layout method, the recommended component configuration consists of 4 x 10-μF capacitors, 1 x 1-μF capacitor, and 1 x 0.1-μF capacitor all on one side of the IC, while a single 0.1-μF capacitor will remain on the opposite side of the IC. Referring to Figure 4-1, removing capacitors C36, C35, C34, and C33 from Pin 9, while adding capacitor C100 to Pin 3, would successfully complete the asymmetrical configuration. Capacitors C21, C23, C37, and C39 are prematurely removed from the design. This represents an asymmetrical design with the majority of the input capacitors on a single pin. It is critical that the high frequency bypass capacitor, C38, remains on Pin 9 as this capacitor prevents excess noise and supresses voltage spikes on SW. The data provided is taken under the TPS54KB20 asymmetrical EVM conditions, using the capacitors shown in Figure 4-1 along with utilizing one VIN rail. It is not recommended to operate the asymmetrical configuration in the RAMP1 setting. At their own discretion, if users intend to remove capacitors on one end of the TPS54KB2x butterfly package, using a single asymmetric VIN pin, the recommended schematic and layout are shown in Figure 4-1, Figure 4-2, and Figure 4-3.

The asymmetrical layout guides are for reference purposes if users intend to design their system based on the TPS54KB20 asymmetrical butterfly footprint. Figure 4-2 and Figure 4-3 are PCB layout images containing red marking on the capacitors recommended for removal to achieve the asymmetrical configuration.