SNAA386 November   2023 CDCE6214 , CDCE6214-Q1 , CDCE6214Q1TM , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK00334 , LMK00334-Q1 , LMK00338 , LMK03318 , LMK03328 , LMK3H0102 , LMK6C , LMK6H , LMKDB1108 , LMKDB1120

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Introduction to PCIe
    1. 2.1 The PCIe Link
  6. 3PCIe Clocking Architectures
    1. 3.1 Common Clock Architecture
    2. 3.2 Separate Reference Architecture
    3. 3.3 Spread Spectrum Clocking
    4. 3.4 PCIe REFCLK Topology
    5. 3.5 Noise Folding
  7. 4PCIe Clocking Specifications
    1. 4.1 REFCLK Output Format
    2. 4.2 PCIe Jitter Requirements
    3. 4.3 PCIe Time Domain Requirements
  8. 5REFCLK Measurement Technique
    1. 5.1 Clock Generator Measurement Results
      1. 5.1.1 PNA Measurement Result without SSC
      2. 5.1.2 PCIe Filtered PNA Result without SSC
      3. 5.1.3 PNA Measurement Result, With SSC
      4. 5.1.4 PCIe Filtered PNA Result, With SSC
      5. 5.1.5 Time Domain PCIe Measurement Result
    2. 5.2 Clock Buffer Measurement Results
      1. 5.2.1 PNA Measurement Result
      2. 5.2.2 PCIe Filtered PNA Result
      3. 5.2.3 Time Domain PCIe Measurement Result
  9. 6Texas Instruments Products with PCIe Compliance
  10. 7Summary
  11. 8References

4.3 PCIe Time Domain Requirements

In addition to the jitter requirements of the REFCLK, there are limitations on various time-domain parameters as well. Table 4-2 summarizes these limits. The limits are not dependent upon PCIe generation or clock architecture.

Table 4-2 PCIe Time Domain Parameters
Parameter PCIe Limit
VCross 250 mV to 550 mV
VHigh +150 mV minimum
VLow –150 mV maximum
|VRingback|(1) 100 mV minimum
Period 9.847 ns to 10.203 ns
Duty Cycle 40% to 60%
VOvershoot +300 mV
VUndershoot –300 mV
Rising Edge Rate 0.6 V/ns to 4 V/ns
Falling Edge Rate 0.6 V/ns to 4 V/ns
(1) The measurement method for PCIe VRingback and Intel® VRingback are not the same. Intel® defines this as the single-ended voltage level that is allowed be reached after an undershoot or overshoot occurs, ±200 mV, before the voltage settles at the VLow or VHigh level, but measured with respect to VLow and VHigh instead of GND

Unless stated otherwise, the parameters in Table 4-2 are measured using the differential waveform, which is typically a math channel of a high-bandwidth oscilloscope configured for subtraction between the two single-ended waveforms. A PCIe REFCLK analysis tool, such as the Texas Instruments PCIe Reference Clock Analysis Tool, uses the individual waveforms and performs the calculation. Table 4-3 describes the parameters in Table 4-2.

Table 4-3 PCIe Parameter Descriptions
Parameter Description
VCross Single-ended voltage when the + and – REFCLK outputs are equal with respect to the system GND, measured on the rising edge of the + output, as measured into an AC load
VHigh High level voltage, as measured into an AC load
VLow Low level voltage, as measured into an AC load
VRingback As measured into an AC load, the voltage level that is allowed be reached after an undershoot or overshoot occurs, before the voltage settles at the VLow or VHigh level, measured from GND
Period Time for a full clock cycle, as measured between rising clock edges, including jitter and SSC
Duty Cycle Percentage of time that clock is held high in relation to full clock period
VOvershoot Overshoot of voltage on rising clock edges, as measured into an AC load
VUndershoot Undershoot of voltage on falling clock edges, as measured into an AC load
Rising Edge Rate The rate at which rising clock edges transition from –150 mV to +150 mV, as measured into an AC load
Falling Edge Rate The rate at which rising clock edges transition from +150 mV to –150 mV, as measured into an AC load

VOvershoot, VUndershoot, and VRingback can appear to violate the PCIe specification when the outputs are improperly terminated, resulting in reflections. Matching the impedance as specified by the REFCLK source and the receiver is critical for minimizing reflections. Refer to Termination Guidelines for Differential and Single-Ended Signals for guidance on properly terminating REFCLK.