SNLU324 March   2023

 

  1.   Abstract
  2.   Trademarks
  3. 1Hardware Description and Setup
    1. 1.1 Required Hardware
    2. 1.2 General Hardware Test Setup Procedure
    3. 1.3 Hardware Configuration to Use External 25 MHz Oscillator for CAL_CLK_IN
  4. 2Software Description
    1. 2.1 Software Installation Sequence
    2. 2.2 Latte Functional Overview
    3. 2.3 Useful Latte Short-Cuts
    4. 2.4 DS560DF410EVM Initialization Through the Latte GUI
      1. 2.4.1 Connect Latte to Board
      2. 2.4.2 Compile Libraries
      3. 2.4.3 Example: Programming DS560DF410EVM for 26.5625 GBd PAM4 Test Case
      4. 2.4.4 Retimer Configuration
      5. 2.4.5 Retimer Useful Functions (Contained in the usefulFunctions.py Latte Script)
      6. 2.4.6 Vertical Eye Monitor
  5. 3Related Documentation
    1. 3.1 Supplemental Content
  6. 4EVM Cable Assemblies

1.2 General Hardware Test Setup Procedure

  1. Check the EVM jumper settings to confirm the settings match Figure 1-1.
  2. Connect a 5 V power supply to the power jack (PWR_JACK), connector J26 on the DS560DF410EVM board.
  3. Check the DS2 (PWR) LED to confirm the LED light is on.
  4. Connect the USB Type Mini-B Cable from the PC to the USB port (J1) of the EVM.
  5. Check the DS4 (USB_PWR) LED.
  6. The 5 V voltage is regulated down to 3.3 V on the EVM (refer to Figure 1-2).
    • The 3.3 V supply is used to derive the 1.2 V and 1.8 V rails for the DS560DF410 retimer.
    • In addition, the 3.3 V voltage directly powers up the EEPROM, FTDI USB interface chip and level shifter devices.
    • VDD 1.2 V is powered up first and secondly the VDD 1.8 V.
    • VDD 1.2 V uses a DC-DC regulator, while the VDD 1.8 V is regulated through the LDO.
  7. Check the DS1 LED (3.3 V) to confirm the LED is on.
  8. The default EVM jumper settings are for using the onboard CAL_CLK_IN 25 MHz oscillator option. If using the external clock signal option, then connect the external clock signal to the retimer CAL_CLK_IN pin through board connector J100.

Recommended CAL_CLK_IN external signal characteristics

  • 1.8 V LVCMOS compatible clock or sinusoidal signal
  • 25 MHz frequency ± 100 PPM
Figure 1-2 DS560DF410EVM Power Tree