SNVA856B May   2020  – October 2022 LM63615-Q1 , LM63625-Q1 , LM63635-Q1 , LMR33620 , LMR33620-Q1 , LMR33630 , LMR33630-Q1 , LMR33640 , LMR36006 , LMR36015 , TPS54360B , TPS54560B

 

  1.   Working With Inverting Buck-Boost Converters
  2.   Trademarks
  3. Introduction
  4. Inverting Buck-Boost Converter
  5. Basic Operation
  6. Operating Considerations of a Buck Based Inverting Buck-Boost
    1. 4.1 Voltage Stress
    2. 4.2 Current Stress
    3. 4.3 Power Loss and Efficiency
    4. 4.4 Small Signal Behavior
      1. 4.4.1 Measuring IBB Bode Plots
      2. 4.4.2 Testing Load Transients on an IBB
      3. 4.4.3 Simulation
  7. Component Selection for the IBB
    1. 5.1 Inductor Selection
    2. 5.2 Capacitor Selection
    3. 5.3 External Feed-back Divider
  8. General Considerations
  9. Auxiliary Functions
    1. 7.1 Enable Input Level Shift
    2. 7.2 Synchronizing Input Level Shift
    3. 7.3 Power-Good Flag Level Shift
    4. 7.4 Output Clamp
    5. 7.5 Output Noise Filtering
  10. Design Examples
    1. 8.1 Converting +12 V to –5 V at 3 A
    2. 8.2 Converting +5 V to –5 V at 1 A
  11. Summary
  12. 10References
  13. 11Revision History

Power-Good Flag Level Shift

Many applications require a "power-good" or "reset" flag from the DC/DC converter to alert the µC that the output voltage is within specification. The circuits shown in Figure 7-3 can be used to level shift the status flag to the system ground.

GUID-C47FBAD0-4F0C-4DE6-9E04-FE3B5DCA161C-low.gif Figure 7-3 Power-Good Flag Level Shifters

The circuit on the left is simple, however the PGOOD signal swings below ground by a diode drop. The circuit on the right is slightly more complicated, giving a PGOOD signal that swings to zero volts. In either case the PGOOD signal swings high to the user defined VLOGIC level. Be sure to check the Absolute Maximum Rating on the power good pin from the buck data sheet. For the circuit on the left, the power good pin must withstand VLOGIC + |VOUT|. For the other design the power good must withstand |VOUT|.