SWRU612 December   2023 CC3300 , CC3301 , CC3351

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
  5. 2Schematic Considerations
    1. 2.1 Schematic Reference Design
    2. 2.2 Power Supply
      1. 2.2.1 Power Input/Output Requirements
      2. 2.2.2 Power-Up Sequence
        1. 2.2.2.1 SOP Modes
    3. 2.3 Clock Source
      1. 2.3.1 Fast Clock
      2. 2.3.2 Slow Clock
        1. 2.3.2.1 Slow Clock Generated Internally
        2. 2.3.2.2 Slow Clock Using an External Oscillator
    4. 2.4 Radio Frequency (RF)
    5. 2.5 Digital Interfaces
      1. 2.5.1 Reset
      2. 2.5.2 Secure Digital Input Output (SDIO)
        1. 2.5.2.1 SDIO Timing Diagram - Default Speed
        2. 2.5.2.2 SDIO Timing Diagram - High Speed
      3. 2.5.3 Serial Peripheral Interface (SPI)
        1. 2.5.3.1 SPI Timing Diagram
      4. 2.5.4 Universal Asynchronous Receiver-Transmitter (UART)
      5. 2.5.5 Serial Wire Debug (SWD)
      6. 2.5.6 Coexistence
  6. 3Layout Considerations
    1. 3.1 Layout Reference Design
      1. 3.1.1 Reference Design Layout
      2. 3.1.2 BP-CC3301 Design Layout
      3. 3.1.3 M2-CC3301 Design Layout
    2. 3.2 IC Thermal Pad
    3. 3.3 Radio Frequency (RF)
    4. 3.4 XTAL
    5. 3.5 Power Supplies
    6. 3.6 SDIO

2.3.1 Fast Clock

The CC330x device supports a crystal-based fast clock (XTAL). The crystal is fed directly between HFXT_P and HFXT_M pins with appropriate loading capacitors and a 150Ω resistor. See the design requirements below:

  1. Provide 150Ω resistor on HFXT_P (pin 6) close to the device and before the XTAL.
  2. XTAL must be connected across HFXT_P (pin 6) and HFXT_M (pin 7).
  3. Provide load capacitors (6.8pF) at both the pins of the XTAL. Note that the recommended load capacitor of 6.8pF is based on TI board layout.
  4. Tuning of the load capacitance may be required depending on customer board layout.

    For further guidance on this topic, see Simplelink Frequency Tuning.

The Fast Clock component must meet the requirements shown in Table 2-3.

Table 2-3 External Fast Clock XTAL Specifications
Parameter Test Conditions MIN TYP MAX Unit
Supported frequencies 40 MHz
Frequency accuracy Initial + temperature + aging ± 25 ppm
Load Capacitance, CL (1) 5 13 pF
Equivalent series resistance, ESR 30 Ω
Drive level 100 μW
(1) Load capacitance, CL= [C1*C2] / [C1 + C2] + CP, where C1, C2 are the capacitors connected on HFXT_P and HFXT_M, respectively, and CP is the parasitic capacitance (typically 1 to 2 pF). For example, for C1 = C2 = 6.2pF and CP = 2pF, then CL = 5pF.