The TSW14DL3200EVM is designed for plug-and-play evaluation with the DAC12DL3200EVM and ADC12DL3200EVM. This provides a capability for prototyping or testing a low-latency LVDS-based DAC transmitter or ADC receiver, or both simultaneously.

TI takes two approaches for measuring the overall end-to-end latency of the DAC12DL3200 device.

Approach 1: Figure 1-2 illustrates this approach where the test signal is fed into the front end of the ADC12DL3200 device and the samples are extracted and collected by the FPGA. These samples are then forwarded to the DAC12DL3200 which generates the resultant output signal (delayed version of the input test signal). The IO architecture of the Xilinx UltraScale enables extremely high-speed data rates by trading off latency for throughput. At bit-rates over 1.2Gbps, the SERDES blocks in the FPGA implement asynchronous clock domain crossing (both at the ADC and the DAC side). In addition, there is a possibility of bit-slips between data lanes of the ADC and the outputs of the receiving SERDES blocks in the FPGA. These are compensated for with an additional layer of buffering inside the FPGA. The total sum of all of these domain crossing and data-ordering-related delays result in an end-to-end latency of 285 ns. Of this, the DAC12DL3200 contributes approximately 6 ns of latency (see the data sheet spec), while the ADC12DL3200 adds a latency of approximately 8 ns. The remaining delay is from the FPGA logic used.

Approach 2: To minimize the delay through the FPGA and obtain a true representation of the latency of the data converters, a simplified setup is created, where the FPGA is used as a combinatorial pass-through device. The FPGA logic passes just the MSB output of the ADC (through the FPGA) to the MSB input of the DAC. The FPGA does not carry out any re-timing of the signals to avoid any non-deterministic delays on account of clock domain crossing. Using this setup, the measured combined latency of ADC12DL3200 + FPGA + DAC12DL3200 + Device EVM routing is 32.8 ns .