SBAU374A May   2021  – May 2022 DAC12DL3200

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Low Latency Evaluation of Receive and Transmit
    2. 1.2 Related Documentation
      1.      Technical Reference Documents
      2.      TSW14DL3200EVM and ADC12DL3200EVM Operation
  4. 2Equipment
    1. 2.1 Evaluation Board Feature Identification Summary
    2. 2.2 Required Equipment
  5. 3Setup Procedure
    1. 3.1  Install the High Speed Data Converter (HSDC) Pro Software
    2. 3.2  Install the Configuration GUI Software
    3. 3.3  Connect the DAC12DL3200EVM and TSW14DL3200EVM
    4. 3.4  Connect the Power Supplies to the Boards (Power Off)
    5. 3.5  Connect the Signal Generators to the EVM (*RF Outputs Disabled Until Directed)
      1. 3.5.1 If External Clocking is Used (Optional)
    6. 3.6  Turn On the TSW14DL3200EVM 12-V Power and Connect to the PC
    7. 3.7  Turn On the DAC12DL3200EVM 5-V Power Supply and Connect to the PC
    8. 3.8  Turn On the Signal Generator RF Outputs
    9. 3.9  Open the DAC12DL3200EVM GUI and Program the DAC and Clocks for Single Channel, NRZ Mode 2 Operation
    10. 3.10 Open the HSDC Software and Load the FPGA Image to the TSW14DL3200EVM
    11. 3.11 DxSTRB Timing Adjustment
  6. 4Other Modes of Operation
    1. 4.1 Single-Channel RF Mode 2 (2nd Nyquist Zone)
    2. 4.2 Dual-Channel Output Mode 0
    3. 4.3 Dual Channel Mode1 Setup
    4. 4.4 Dual-Channel 2xRF Mode 0 DAC Setup
    5. 4.5 Direct Digital Synthesis Mode
  7. 5Register Log File
  8. 6Device Configuration
    1. 6.1 Tab Organization
    2. 6.2 Low-Level Control
  9.   A Troubleshooting the DAC12DL3200EVM
  10.   B DAC12DL3200EVM Onboard Clocking Configuration

Introduction

The DAC12DL3200 is a very low latency, dual-channel, 12-bit RF sampling digital-to-analog converter (DAC), capable of operating at sampling rates up to 3.2 Giga-samples per second (GSPS) in dual-channel mode, or 6.4 GSPS in single-channel mode. The DAC can transmit signal bandwidths beyond 2 GHz at carrier frequencies approaching 8 GHz when using multi-Nyquist output modes. The DAC12DL3200EVM device input data is transmitted over a high-speed LVDS interface. This evaluation board also includes the following important features:

  • Transformer-coupled output allowing for a single-ended 50-Ω output signal up to 8 GHz
  • The LMX2592 clock synthesizer as an option to generate the DAC sampling clock
  • Transformer-coupled input clock option (board default setup) for quick setup with external clock sources
  • LMK04828 clock synthesizer for DAC SYSREF and FPGA reference clock source
  • Device register programming through USB connector and FTDI USB-to-SPI bus translator
  • High-speed LVDS data input over a 400-pin FMC interface connector
GUID-20210330-CA0I-RB9D-SP1M-2JNHW8WMKRQZ-low.jpgFigure 1-1 DAC12DL3200EVM

The TI TSW14DL3200EVM pattern generator, when used with the TI High-Speed-Data-Converter (HSDC) Pro Software GUI, is used to send LVDS data test patterns to the DAC12DL3200EVM.

With proper hardware selection in the HSDC Pro software, the TSW14DL3200EVM is automatically configured to support the different modes of operation of the DAC12DL3200. The interface provides LVDS output data up to 1600 MSPS.