SBAU436A January   2024  – February 2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Analog Input Options
      1. 2.1.1 Differential SMA Inputs
      2. 2.1.2 Single-Ended SMA Inputs
      3. 2.1.3 Differential Input Pins
    2. 2.2 Power Supplies
    3. 2.3 ADC Connections and Decoupling
    4. 2.4 ADC Input Amplifiers
    5. 2.5 VCOM Buffer
    6. 2.6 Voltage Reference
    7. 2.7 Clock Tree
    8. 2.8 Digital Interfaces
  9. 3Software
    1. 3.1 ADS1278EVM Software Installation
  10. 4Implementation Results
    1. 4.1 Hardware Connections
    2. 4.2 Optional EVM Configuration
    3. 4.3 GUI Settings for ADC Control
    4. 4.4 Time Domain Display
    5. 4.5 Frequency Domain Display
    6. 4.6 Histogram Display
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7References
  14. 8Revision History

2.7 Clock Tree

The onboard PLL of the PHI controller board provides the default clock for the ADS1278 EVM. This clock is configurable for arbitrary frequencies using the Clock Settings dialogue in the GUI as described in Section 4.3. The ADS1278 EVM can also be configured to use an onboard hardware oscillator or an external clock. Figure 3-8 shows the different on-board clock options for the ADS1278 EVM.

GUID-20231113-SS0I-RDVQ-74FX-GVPNBVNN31RP-low.svgFigure 2-8 Clock Source Circuit

When jumper JP2 is in the default position (1-2), the CLK pin on the ADS1278 is routed to the PHI clock output. Change the shunt on jumper JP2 to position 2-3 if the ADS1278 EVM is used with the onboard clocking options. Moving jumper JP1 to position 1-2 disables the local 27MHz oscillator (Y1) on the ADS1278 EVM, allowing an external clock supplied on the SMA connector (J7).

To use an external clock source, apply a CMOS square-wave signal with an amplitude equal to IOVDD (3.3V) and a frequency within the specified range of the ADS1278. Additionally, the appropriate clock frequencies must be programmed into the Clock Settings dialogue in the GUI to verify the communication speed is correct.

Note: Writing the same frequency repeatedly to the onboard PLL of the PHI controller sometimes causes the PLL to become stuck at that frequency. To prevent this, the GUI software prevents repeated writes of the same frequency to the PLL. However, the PLL has a limited frequency resolution and repeated writes to different frequencies can cause the PLL to become stuck if the entered frequencies are coerced to the same frequency. If this occurs, then disconnect and reconnect the GUI to reset the PLL.