SLAAED9 November 2023 TAA5412-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1
The latched registers are set up to mirror the live registers. The latched status of each diagnostic fault is reported by the channel in P1_R54 to P1_R57, and a latched summary of all channels is reported in CHx_LTCH, P1_R53. The latched registers are latched when the associated bit in the live fault registers transitions from a 0 to a 1 and the conditions set in the fault filtering registers are met. A transition of any bit in the latched register from a 0 to 1 triggers an interrupt request. By default, latched registers are cleared after reading only if the fault is no longer present and the associated live register reports 0, otherwise the register remains latched. There is an additional mode in which the latched registers clears, regardless of the status of the associated live registers. This feature is useful for identifying unique faults as only one interrupt is generated per fault. This feature can be enabled by setting the LTCH_CLR_ON_READ bit to 1 in the INT_CFG register.