The following paragraphs are intended to guide a user through the steps necessary to configure the TAS2505.

Step 1

The system clock source (master clock) and the targeted DAC sampling frequency must be identified. Depending on the targeted performance, the decimation filter type (A or B) and DOSR value can be determined:

• Filter A should be used for 48-kHz high-performance operation; DOSR must be a multiple of 8.
• Filter B should be used for up to 96-kHz operations; DOSR must be a multiple of 4.

In all cases, DOSR is limited in its range by the following condition:

Based on the identified filter type and the required signal processing capabilities, the appropriate processing block can be determined from the list of available processing blocks (PRB_P1, PRB_P2 and PRB_P3).

Based on the available master clock, the chosen DOSR and the targeted sampling rate, the clock divider values NDAC and MDAC can be determined. If necessary, the internal PLL can add a large degree of flexibility.

In summary, CODEC_CLKIN (derived directly from the system clock source or from the internal PLL) divided by MDAC, NDAC, and DOSR must be equal to the DAC sampling rate DAC_fS. The CODEC_CLKIN clock signal is shared with the DAC clock generation block.

NDAC and MDAC can be chosen independently in the range of 1 to 128. In general, NDAC should be as large as possible as long as the following condition can still be met:

RC is a function of the chosen processing block and is listed in Table 3-3.

The common-mode voltage setting of the device is determined by the available analog power supply. This common-mode (input common-mode) value is common across the ADC, DAC and analog bypass path. The output common-mode setting is determined by the available analog power supplies (AVdd) and the desired output-signal swing.

At this point, the following device specific parameters are known:

PRB_Rx, DOSR, NDAC, MDAC, input and output common-mode values.

If the PLL is used, the PLL parameters P, J, D and R are determined as well.

Step 2

Setting up the device with register programming:

The following list gives a sequence of items that must be executed in the time between powering the device up and reading data from the device:

1. Define starting point:
   1. Power up applicable external power supplies
   2. Set register page to 0
   3. Initiate SW reset
2. Program Clock Settings
   1. Program PLL clock dividers P, J, D and R (if PLL is necessary)
   2. Power up PLL (if PLL is necessary)
   3. Program and power up NDAC
   4. Program and power up MDAC
   5. Program OSR value
   6. Program I2S word length if required (16, 20, 24, or 32 bits)
   7. Program the processing block to be used
   8. Miscellaneous page 0 controls
   At this point, at the latest, the analog power supply must be applied to the device
3. Program Analog Blocks
   1. Set register page to 1
   2. Disable coarse AVDD generation
   3. Enable Master Analog Power Control
   4. Program common-mode voltage
   5. Program headphone-specific de-pop settings (if a headphone driver is used)
   6. Program routing of DAC output to the output amplifier (headphone and lineout or speaker)
4. Apply waiting time determined by the de-pop settings and the soft-stepping settings of the driver gain or poll page 1, register 63
5. Power up DAC
   1. Set register page to 0
   2. Power up DAC channels and set digital gain
   3. Unmute digital volume control
6. Power up Output Drivers
   1. Unmute and set gain of output drivers
   2. Power up output drivers

Detailed examples can be found from Section 5.1 to Section 5.6.