SLVUCO6 june   2023 TPSI2072-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4.   General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  5. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
  6. 2Connection Descriptions
  7. 3Test Equipment
  8. 4Recommended Test Setup
    1. 4.1 Waveforms
    2. 4.2 VS1_ADC and VS2_ADC Voltage Dividers
  9. 5Schematic
  10. 6PCB Layout
  11. 7Interlayer Stitching Capacitor
    1. 7.1 Interlayer Stiching Capacitors & EMI Performance Improvements
    2. 7.2 VS1_ADC and VS2_ADC Voltage Dividers
  12. 8Bill of Materials
  13. 9Revision History

2 Connection Descriptions

Table 2-2 shows an overview of the input/output connectors. Table 2-2 shows the test points and jumpers.

Table 2-1 Input and Output Connector Descriptions
ConnectorLabelDescription
J1

HV1

Secondary side positive input 1

J2

SM

Voltage sense output

J3

HV–

Secondary side negative input

J4

VDD

Primary

Side supply

J5

GND

Primary

Side GND

J6

EN1_EXTERNAL

External

Enable 1 Signal

J8

EN2_EXTERNAL

External Enable 2 signal

J10

HV2

Secondary side positive input 2

Table 2-2 Test Point and Jumper Descriptions
Test Point, JumperLabelDescription
TP1VDD

Primary side supply test point

TP2EN1_EXTERNALEN1_EXTERNAL test point
TP3, TP4GNDPrimary side ground test point
TP5S1

Secondary side HV1 voltage after resistor chain

TP6

SM

Thermal Pin
TP7

S2

Secondary side HV2 voltage after resistor chain

TP8

HV-

HV– secondary side test point

TP9

EN2_EXTERNAL

EN2_EXTERNAL test point
J7

EN1_X/EN1/VDD

Connects EN1_X to EN1,

or EN1 to VDD. Allows for external enable signal to be used instead of EN1 being signaled by VDD

J9

EN2_X/EN2/VDDConnects EN2_X to EN2,

or EN2 to VDD. Allows for external enable signal to be used instead of EN2 being signaled by VDD

J11

Stitching Capacitor Jumper

Connects interlayer stitching capacitor (20 pF) between primary and secondary ground to improve EMI performance.