SNLA423 March   2023 DP83826E

 

  1. 1Trademarks
  2. 2DP83826 Application Overview
  3. 3Troubleshooting the Application
    1. 3.1 Read and Check Register Values
    2. 3.2 Schematic and Layout Checklist
    3. 3.3 Component Checklist
    4. 3.4 Peripheral Pin Checks
      1. 3.4.1 Power Supplies
      2. 3.4.2 Probe the XI Clock
      3. 3.4.3 Probe the RESET_N Signal
      4. 3.4.4 Probe the Strap Pins During Initialization
      5. 3.4.5 Probe the Serial Management Interface Signals (MDC, MDIO)
      6. 3.4.6 Probe the MDI Signals
    5. 3.5 Link Quality Check
    6. 3.6 Built-In Self Test with Various Loopback Modes
    7. 3.7 Debugging MAC Interface
    8. 3.8 Tools and References
      1. 3.8.1 DP83826 Register Access
      2. 3.8.2 Extended Register Access
      3. 3.8.3 Application Note References
  4. 4Conclusion
  5. 5Revision History

3.1 Read and Check Register Values

Read the registers and verify the default values shown in the data sheet. Note that the initial values of some registers can vary based on strap options.

The expected register values for PHY operation and link in 10/100 Mbps with auto-negotiation enabled are shown below.

Table 3-1 DP83826 Register Value References
REGISTER ADDRESS REGISTER VALUE
10 Mbps 100 Mbps
0x0000 3100 3100
0x0001 786D 786D
0x0002 2000 2000
0x0003 A130 A130
0x0004 0041 01E1
0x0005 (1) 41E1 41E1
0x0006 0007 0007
0x0007 2001 2001
0x0008 0000 0000
0x0009 0000 0000
0x000A 0100 0100
0x000B 0000 0000
0x000D 0000 0000
0x000E 0000 0000
0x000F 0000 0000
0x0010 (2) 4717 or 0017 4715 or 0715
0x0011 0108 0108
0x0012 7400 7400
0x0013 2800 2800
0x0014 0000 0000
0x0015 0000 0000
0x0016 0100 0100
0x0017 0041 0041
0x0018 0480 0480
0x0019 C000 CC00
0x001A 0000 0000
0X001B 007D 007D
0X001B 05EE 05EE
0X001C 0000 0000
0x001E 0002 0102

With the PHY linked in a given speed, use these values as a reference to identify any variance from the expected operation. Note that not all registers need to be the same, for example .

  1. The value of Register 0x0005 depends on the link partner's capabilities.
  2. The '4' or '0' difference in the MSB of Register 0x0010 is due to bit 14 MDI/MDIX Mode, doesn't affect anything. The significant difference is the '7' or '5' as the LSB, this tells you the Speed Status.

Example: After powering and linking the PHY in 10 Mbps, register 0x0010 is read at hex value 0017. Meaning Bits [4, 2, 1, 0] are high. These bits confirm: Auto-Negotiation is complete, Full-Duplex, 10 Mbps Mode, and valid link established.

Repeating this process for any values distinct from the expected values shown in the table will help diagnose the exact state of the PHY for any encountered issues.