SPRAAV1C May 2009 – March 2020 AM3703 , AM3715 , OMAP3503 , OMAP3515 , OMAP3525 , OMAP3530
One huge benefit of PoP is the elimination of the high-speed, balanced transmission lines between the processor and memory. The external memory’s data and control lines no longer have to be routed out from under the processor. This is a huge savings in both time and the number of layers. This also impacts your pad and layer stackup decisions. OEMs have quickly adopted PoP as their processor/memory package of choice for these reasons.
It is possible to use a 6-layer stack and route all of the connections without requiring buried vias. For the BeagleBoard, relatively common VIP technology was used. There are several suitable layer setups; the one described below was used in the BeagleBoard. This format is also popular because it allows sensitive clock signals or relatively high-speed lines to be routed between power planes.
Layer 1 | Signal (Top Copper) |
Layer 2 | Ground |
Layer 3 | Signal |
Layer 4 | Signal |
Layer 5 | Power |
Layer 6 | Signal (Bottom Copper) |
Package footprints and pad stacks are the next important item to consider. Proper definitions and strict adherence to clearance plays a key role in the development of high yield PoP designs.