SPRACC0A November   2017  – November 2020 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1

 

  1.   Trademarks
  2. 1 Introduction and Scope
  3. 2 SRAM Bit Array
  4. 3 Sources of SRAM Failures
    1. 3.1 Manufacturing Defects
      1. 3.1.1 Time Zero Fails
      2. 3.1.2 Latent Fails
    2. 3.2 Circuit Drift With Usage
    3. 3.3 Circuit Overstress
    4. 3.4 Soft Errors
      1. 3.4.1 Radioactive Events
      2. 3.4.2 Dynamic Voltage Events
      3. 3.4.3 Summary of Error Sources
  5. 4 Methods for Managing Memory Failures in Electronic Systems
    1. 4.1 Start-Up Testing
    2. 4.2 In-System Testing
    3. 4.3 Parity Detection
    4. 4.4 Error Detection and Correction (EDAC)
    5. 4.5 Redundancy
  6. 5 Comparisons and Conclusions
  7. 6  C2000 Memory Types Example
    1. 6.1 TMS320F2837xD
  8. 7 Memory Types
    1. 7.1 Dedicated RAM (Mx and Dx RAM)
    2. 7.2 Local Shared RAM (LSx RAM)
    3. 7.3 Global Shared RAM (GSx RAM)
    4. 7.4 CPU Message RAM (CPU MSGRAM)
    5. 7.5 CLA Message RAM (CLA MSGRAM)
  9. 8 Summary
  10. 9 References
  11. 10Revision History

7.3 Global Shared RAM (GSx RAM)

RAM blocks which are accessible from both the CPU and DMA are called global shared RAMs (GSx RAMs). Each shared RAM block can be owned by either CPU subsystem based on the configuration of respective bits in the GSxMSEL register.

All GSx RAM blocks have parity.

When a GSx RAM block is owned by a CPU subsystem, the CPUx and CPUx.DMA will have full access to that RAM block whereas the other CPUy and CPUy.DMA will only have read access (no fetch/write access).

Table 7-3 shows the master access for the GSx RAM.

Table 7-3 Master Access for GSx RAM
(With Assumption That all Other Access Protections are Disabled)
GSxMSEL CPU Instruction Fetch Read Write CPUx.DMA Read CPUx.DMA Write
0 CPU1 Yes Yes Yes Yes Yes
CPU2 – Yes – Yes –
1 CPU1 – Yes – Yes –
CPU2 Yes Yes Yes Yes Yes

The GSx RAMs have access protection (CPU write/CPU fetch/DMA write).