SPRUJ93 august   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1.     Preface: Read This First
      1. 1.1.1 Sitara™ MCU+ Academy
      2. 1.1.2 If You Need Assistance
      3. 1.1.3 Important Usage Notes
    2. 1.1 Introduction
    3. 1.2 Kit Contents
    4. 1.3 Specification
    5. 1.4 Device Information
    6. 1.5 HSEC 180-pin Control Card Docking Station
    7. 1.6 Security
  6. 2Hardware
    1. 2.1  Functional Block Diagram
    2. 2.2  Component Identification
    3. 2.3  Power Requirements
      1. 2.3.1 Power Input Using USB Type-C Connector
      2. 2.3.2 Power Status LEDs
      3. 2.3.3 Power Tree
      4. 2.3.4 Power Sequence
      5. 2.3.5 PMIC
    4. 2.4  Reset
    5. 2.5  Clock
    6. 2.6  Boot Mode Selection
    7. 2.7  JTAG Path Selection
    8. 2.8  Header Information
    9. 2.9  GPIO Mapping
    10. 2.10 Push Buttons
    11. 2.11 Test Points
    12. 2.12 Interfaces
      1. 2.12.1  Memory Interface
        1. 2.12.1.1 QSPI
        2. 2.12.1.2 Board ID EEPROM
      2. 2.12.2  Ethernet Interface
        1. 2.12.2.1 RGMII
        2. 2.12.2.2 PRU-ICSS
        3. 2.12.2.3 LED Indication in RJ45 Connector
      3. 2.12.3  I2C
      4. 2.12.4  Industrial Application LEDs
      5. 2.12.5  SPI
      6. 2.12.6  UART
      7. 2.12.7  MCAN
      8. 2.12.8  FSI
      9. 2.12.9  JTAG
      10. 2.12.10 Test Automation Header
      11. 2.12.11 LIN
      12. 2.12.12 MMC
      13. 2.12.13 ADC and DAC
    13. 2.13 HSEC Pinout and Pinmux Mapping
  7. 3Software
    1. 3.1 SDK Installation
  8. 4Hardware Design Files
  9. 5Additional Information
    1. 5.1 Trademarks
    2. 5.2 E1 Design Hardware Modifications
  10. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design

2.12.2.1 RGMII

The AM263x Control Card uses one port of RGMII signals to be connected to a 48-pin Ethernet PHY (DP83TG730SWRHARQ1). The PHY is configured to advertise 1-Gb operation. The Ethernet data signals of the PHY are terminated to a MATEnet Connector. LEDs are used to indicate link status and activity.

GUID-20230515-SS0I-KNSG-R68C-SBM3LZVMDDRR-low.png Figure 2-18 RGMII1 Automotive Ethernet PHY

The Ethernet PHY requires three separate power sources. VSYS_3V3A from the PMIC is filtered using two different ferrite beads to supply voltage to VDDIO and VDDA of the Ethernet PHY. There is a dedicated LDO for the 1.0 V supply for the Ethernet PHY.

There are series termination resistors on the transmit and receive clock signals located near the AM263x SoC.

The MDIO and interrupt signals from the SoC to the PHY require 2.2 kΩ pull up resistors to the I/O supply voltage for proper operation. The interrupt signal is driven by a GPIO signal that is mapped from the AM263x SoC.

The reset signal for the Ethernet PHY is driven by a 2-input AND gate. The AND gate's inputs are a GPIO signal that is generated by the IO Expander and PORz.

The Ethernet PHY uses many functional pins as strap option to place the device into specific modes of operation.

GUID-20230515-SS0I-1J86-V4VQ-GX7HVRXQN8M7-low.png Figure 2-19 RGMII1 Automotive Ethernet PHY Strapping Resistors
Note: Each strapping has an internal pull down resistance.
Table 2-16 RGMII1 Gigabit Ethernet PHY Strapping Resistors
Functional Pin Default Mode Mode in CC Function
RX_D0 0 0 RGMII (Align Mode)
RX_D1 0 0
RX_D2 0 1
RX_CTRL 0 0 PHY Address: 0x0000
STRP_1 0 0
LED_0 0 0 MS: Peripheral
LED_1 0 0 AUTO: Autonomous