SPRUJ93 august   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1.     Preface: Read This First
      1. 1.1.1 Sitara™ MCU+ Academy
      2. 1.1.2 If You Need Assistance
      3. 1.1.3 Important Usage Notes
    2. 1.1 Introduction
    3. 1.2 Kit Contents
    4. 1.3 Specification
    5. 1.4 Device Information
    6. 1.5 HSEC 180-pin Control Card Docking Station
    7. 1.6 Security
  6. 2Hardware
    1. 2.1  Functional Block Diagram
    2. 2.2  Component Identification
    3. 2.3  Power Requirements
      1. 2.3.1 Power Input Using USB Type-C Connector
      2. 2.3.2 Power Status LEDs
      3. 2.3.3 Power Tree
      4. 2.3.4 Power Sequence
      5. 2.3.5 PMIC
    4. 2.4  Reset
    5. 2.5  Clock
    6. 2.6  Boot Mode Selection
    7. 2.7  JTAG Path Selection
    8. 2.8  Header Information
    9. 2.9  GPIO Mapping
    10. 2.10 Push Buttons
    11. 2.11 Test Points
    12. 2.12 Interfaces
      1. 2.12.1  Memory Interface
        1. 2.12.1.1 QSPI
        2. 2.12.1.2 Board ID EEPROM
      2. 2.12.2  Ethernet Interface
        1. 2.12.2.1 RGMII
        2. 2.12.2.2 PRU-ICSS
        3. 2.12.2.3 LED Indication in RJ45 Connector
      3. 2.12.3  I2C
      4. 2.12.4  Industrial Application LEDs
      5. 2.12.5  SPI
      6. 2.12.6  UART
      7. 2.12.7  MCAN
      8. 2.12.8  FSI
      9. 2.12.9  JTAG
      10. 2.12.10 Test Automation Header
      11. 2.12.11 LIN
      12. 2.12.12 MMC
      13. 2.12.13 ADC and DAC
    13. 2.13 HSEC Pinout and Pinmux Mapping
  7. 3Software
    1. 3.1 SDK Installation
  8. 4Hardware Design Files
  9. 5Additional Information
    1. 5.1 Trademarks
    2. 5.2 E1 Design Hardware Modifications
  10. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design

2.4 Reset

Figure 3-10 shows the reset architecture of the AM263x Control Card.

GUID-20230515-SS0I-SSSW-QRQZ-NNL6LZKMK7MG-low.png Figure 2-10 Reset Architecture

The AM263x SoC has the following resets:

  • PORz is the Power-On-Reset for the MAIN Domain.
  • WARMRESETn is the Warm Reset to MAIN Domain.

GUID-20230515-SS0I-F89G-WC00-KM5LRVXV8VMR-low.png Figure 2-11 PORz Reset Signal Tree

The PORz signal is driven by a 3-input AND gate that generates a power on reset for the MAIN domain when:

  • The PMIC drives the NRES, MCU Reset output signal low.
  • The Voltage Monitor (TPS37042A3OFDDFRQ1) drives either RESET1 or RESET2 when VSYS_3V3A or VSYS_1V2 respectively are outside of the defined boundaries. For VSYS_3V3A, RESET1 is asserted when SENSE1 is either 8% above or below 3.3 V (including device accuracy). For VSYS_1V2, RESET2 is asserted when SENSE2 is either 5% above or below 1.2 V (including device accuracy.
  • The user push button (SW2) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TA_PORZn) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero and so the PORz signal connects to the PMOS drain which is tied directly to ground.

The PORz signal is tied to:

  • AM263x SoC PORz input
  • RGMII1 Ethernet PHY reset
  • ICSSM1 Gigabit Ethernet PHY reset
  • ICSSM2 Industrial Ethernet PHY reset
  • BOOTMODE buffer output enable

GUID-20220419-SS0I-1B9V-PSVC-LXLN1HZWPJ9R-low.png Figure 2-12 WARMRESETn Reset Signal Tree

The WARMRESETn signal creates a warm reset to the MAIN domain when:

  • The user push button (SW4) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TA_RESETz) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero and so the RESETz signal connects to the PMOS drain which is tied directly to ground.

The WARMRESETn signal is tied to:

  • AM263x SoC WARMRESETN output
  • RESETz signal created from push button + PMOS logic
  • IO Expander reset
  • Micro SD reset

The AM263x Control Card also has an external interrupt to the SoC, INTn, that occurs when:

  • The user push button (SW1) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TA_GPIO1) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero, connecting the INTn signal to he PMOS drain tied directly to ground.