TIDUF03 December   2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 System Design Theory
      1. 2.2.1 Detection Principals
      2. 2.2.2 Saturation
      3. 2.2.3 General Mode of Operation
    3. 2.3 Highlighted Products
      1. 2.3.1 DRV8220
      2. 2.3.2 OPAx202
      3. 2.3.3 TLVx172
      4. 2.3.4 TLV7011
      5. 2.3.5 INA293
      6. 2.3.6 SN74LVC1G74
      7. 2.3.7 TLV767
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1  Board Overview
      2. 3.1.2  Filter Stage
      3. 3.1.3  Differential to Single-Ended Converter
      4. 3.1.4  Low-Pass Filter
      5. 3.1.5  Full-Wave Rectifier
      6. 3.1.6  DC Offset Circuit
      7. 3.1.7  Auto-Oscillation Circuit
        1.       31
      8. 3.1.8  DRV8220 H-Bridge
      9. 3.1.9  Saturation Detection Circuit
      10. 3.1.10 H-Bridge Controlled by DFF
      11. 3.1.11 MCU Selection
      12. 3.1.12 Move Away From Timer Capture
      13. 3.1.13 Differentiating DC and AC From the Same Signal
      14. 3.1.14 Fluxgate Sensor
    2. 3.2 Software Requirements
      1. 3.2.1 Software Description for Fault Detection
    3. 3.3 Test Setup
      1. 3.3.1 Ground-Fault Simulation
    4. 3.4 Test Results
      1. 3.4.1 Linearity Over Temperature
    5. 3.5 Fault Response Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 Support Resources
    4. 4.4 Trademarks
  10. 5About the Author

3.1.2 Filter Stage

The three goals of filter stage are to gain the ground fault detection signal, filter the noise created by the auto-oscillation circuit, and correct a DC bias inherent to the fluxgate core.

Filter noise in the signal path from the burden resistor to the ADC. Too much noise can trigger false trips. The major source of noise is switching caused by the auto-oscillation circuit generating switching of the DRV8220. The auto-oscillation switching frequency changes with fluxgate sensor permeability, burden resistance, or adjusting the saturation detection circuit. The Hitachi nanocrystalline cores used for testing ranged from 600 Hz–800 Hz with a 1-kΩ burden resistor.

During a fault, the filter stage outputs a detectable signal read by the ADC. A fault trip occurs when the filter stage output signal passes a threshold and the MCU determines the fault type, as AC and DC faults have separate trip thresholds adjustable within software.

In this design with a gain of 20 dB, a DC fault of 6-mA outputs a 200-mV offset. An AC fault of 30-mARMS outputs a peak of 600 mV. The gain can be increased, make sure the trip threshold is below the rail of op amps.

Filter stage is designed to gain the fault signal by 20 dB and attenuate frequencies above 70 Hz. Figure 3-3 highlights the receiver circuit that consists of a differential to single-ended active low-pass filter and a full-wave rectifier. A DC offset circuit was added in place of R23 to mitigate the offset of the nanocrystalline core.

GUID-20220727-SS0I-BJGN-RKDP-H9MGQXZRMDSN-low.gif Figure 3-3 Filter Stage Schematic

The filter topology used is the MFB topology (sometimes called infinite gain or Rauch) and is often preferred due to low sensitivity to component variations. The MFB topology creates an inverting second-order stage. This inversion can be a concern in the filter application. The MFB filter circuit can be configured as a low-pass filter, high-pass filter, or band-pass filter based on the component selection. For this application, a fourth-order low-pass filter with a Butterworth response was used.