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74AC16245

AKTIV

Bustransceiver, 16 Bit, mit Tri-State-Ausgängen

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Datenblatt

74AC16245

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Supply voltage (min) (V) 3 Supply voltage (max) (V) 5.5 Number of channels 16 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type CMOS Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family AC Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 3 Supply voltage (max) (V) 5.5 Number of channels 16 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type CMOS Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family AC Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 48 164.358 mm² 15.88 x 10.35
  • Members of the Texas Instruments WidebusTM Family
  • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Configuration Minimizes High-Speed Switching Noise
  • EPIC TM (Enhanced-Performance Implanted CMOS) 1-um Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Thin Shrink Small-Outline (DGG) Package, 300-mil Shrink Small-Outline (DL) Package Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Pin Spacings

    EPIC and Widebus are trademarks of Texas Instruments Incorporated.
  • Members of the Texas Instruments WidebusTM Family
  • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Configuration Minimizes High-Speed Switching Noise
  • EPIC TM (Enhanced-Performance Implanted CMOS) 1-um Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Thin Shrink Small-Outline (DGG) Package, 300-mil Shrink Small-Outline (DL) Package Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Pin Spacings

    EPIC and Widebus are trademarks of Texas Instruments Incorporated.

The 'AC16245 are 16-bit bus transceivers organized as dual-octal noninverting 3-state transceivers designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements

These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction control (DIR) input. The output-enable input (OE\) can be used to disable the devices so that the buses are effectively isolated.

The 74AC16245 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The 54AC16245 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74AC16245 is characterized for operation from -40°C to 85°C.

The 'AC16245 are 16-bit bus transceivers organized as dual-octal noninverting 3-state transceivers designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements

These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction control (DIR) input. The output-enable input (OE\) can be used to disable the devices so that the buses are effectively isolated.

The 74AC16245 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The 54AC16245 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74AC16245 is characterized for operation from -40°C to 85°C.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet 16-Bit Bus Transceivers With 3-State Outputs datasheet (Rev. A) 01 Apr 1996
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
More literature HiRel Unitrode Power Management Brochure 07 Jul 2009
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design und Entwicklung

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