Produktdetails

Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Number of channels 8 IOL (max) (mA) 64 Supply current (max) (µA) 80 IOH (max) (mA) -15 Input type TTL-Compatible CMOS Output type 3-State Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) 0 to 70
Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Number of channels 8 IOL (max) (mA) 64 Supply current (max) (µA) 80 IOH (max) (mA) -15 Input type TTL-Compatible CMOS Output type 3-State Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) 0 to 70
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • BiCMOS Technology With Low Quiescent Power
  • Buffered Inputs
  • Noninverted Outputs
  • Input/Output Isolation From VCC
  • Controlled Output Edge Rates
  • 64-mA Output Sink Current
  • Output Voltage Swing Limited to 3.7 V
  • SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
  • BiCMOS Technology With Low Quiescent Power
  • Buffered Inputs
  • Noninverted Outputs
  • Input/Output Isolation From VCC
  • Controlled Output Edge Rates
  • 64-mA Output Sink Current
  • Output Voltage Swing Limited to 3.7 V
  • SCR Latch-Up-Resistant BiCMOS Process and Circuit Design

The CD74FCT244 and CD74FCT244AT are octal buffer/line drivers with 3-state outputs using a small-geometry BiCMOS technology. The output stages are a combination of bipolar and CMOS transistors that limit the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces the power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 mA.

These devices are organized as two 4-bit buffers/line drivers with separate active-low output-enable (OE\) inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD74FCT244 and CD74FCT244AT are octal buffer/line drivers with 3-state outputs using a small-geometry BiCMOS technology. The output stages are a combination of bipolar and CMOS transistors that limit the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces the power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 mA.

These devices are organized as two 4-bit buffers/line drivers with separate active-low output-enable (OE\) inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet BiCMOS Octal Buffers/Line Drivers With 3-State Outputs datasheet (Rev. B) 25 Jul 2002
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Selection guide Advanced Bus Interface Logic Selection Guide 09 Jan 2001

Design und Entwicklung

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Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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Simulationsmodell

CD74FCT244 Behavioral SPICE Model

SCHM062.ZIP (7 KB) - PSpice Model
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PDIP (N) 20 Optionen anzeigen
SOIC (DW) 20 Optionen anzeigen

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