SN74AHCT1G125

Name: SN74AHCT1G125
Brand: TI
SKU: SN74AHCT1G125
Price: 0.108 USD

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Einzelner Puffer, 4,5 V bis 5,5 V, mit TTL-kompatiblen CMOS-Eingängen und Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat SN74AHCT1G125 Single Bus Buffer Gate With 3-State Output datasheet (Rev. P) (Englisch) PDF | HTML

SN74AHCT1G125

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Datenblatt

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Produktdetails

Technology family

AHCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

IOH (max) (mA)

-8

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

AHCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

IOH (max) (mA)

-8

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SOT-23 (DBV)

8.12 mm² 2.9 x 2.8

SOT-5X3 (DRL)

2.56 mm² 1.6 x 1.6

SOT-SC70 (DCK)

4.2 mm² 2 x 2.1

Operating range of 4.5V to 5.5V
Max tpd of 6ns at 5V
Low power consumption, 10µA max ICC
±8mA output drive at 5V
Inputs are TTL-voltage compatible
Latch-up performance exceeds 250mA per JESD 17

Operating range of 4.5V to 5.5V
Max tpd of 6ns at 5V
Low power consumption, 10µA max ICC
±8mA output drive at 5V
Inputs are TTL-voltage compatible
Latch-up performance exceeds 250mA per JESD 17

The SN74AHCT1G125 device is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable ( OE) input is high. When OE is low, data is passed from the A input to the Y output.

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Andere Nicht invertierende Puffer & Treiber suchen

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Technische Dokumentation

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Alle anzeigen 19

	Typ	Titel		Datum
*	Data sheet	SN74AHCT1G125 Single Bus Buffer Gate With 3-State Output datasheet (Rev. P)	PDF \| HTML	19 Mär 2024
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 Jul 2021
	Selection guide	Little Logic Guide 2018 (Rev. G)		06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)		26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)		22 Jun 2004
	Application note	Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)		02 Dez 2002
	Application note	Texas Instruments Little Logic Application Report		01 Nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	Design guide	AHC/AHCT Designer's Guide February 2000 (Rev. D)		24 Feb 2000
	Product overview	Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)		01 Apr 1998
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		01 Dez 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 Jun 1997
	Application note	Live Insertion		01 Okt 1996

Design und Entwicklung

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