SN74AUP2G00-Q1

Name: SN74AUP2G00-Q1
Brand: TI
SKU: SN74AUP2G00-Q1
Price: 0.289 USD

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2-Kanal, 2 Eingänge, 0,8-V- bis 3,6-V-NAND-Gatter mit geringem Stromverbrauch für die Automobilindus

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Datenblatt

document-pdfAcrobat SN74AUP2G00-Q1 Low-Power Dual 2-Input Positive-NAND Gate datasheet (Englisch)

SN74AUP2G00-Q1

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Datenblatt

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Produktdetails

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

2

Inputs per channel

2

IOL (max) (mA)

4

IOH (max) (mA)

-4

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

100

Rating

Automotive

Operating temperature range (°C)

-40 to 125

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

2

Inputs per channel

2

IOL (max) (mA)

4

IOH (max) (mA)

-4

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

100

Rating

Automotive

Operating temperature range (°C)

-40 to 125

VSSOP (DCU)

8

6.2 mm² 2 x 3.1

Qualified for Automotive Applications
Low Static-Power Consumption
(I_CC = 1.7 µA Maximum)
Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typ at 3.3 V)
Low Input Capacitance (C_i = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot
<10% of V_CC
I_off Supports Partial-Power-Down Mode Operation
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 5.9 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Qualified for Automotive Applications
Low Static-Power Consumption
(I_CC = 1.7 µA Maximum)
Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typ at 3.3 V)
Low Input Capacitance (C_i = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot
<10% of V_CC
I_off Supports Partial-Power-Down Mode Operation
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 5.9 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

The SN74AUP2G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

The SN74AUP2G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technische Dokumentation

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Alle anzeigen 6

	Typ	Titel		Datum
*	Data sheet	SN74AUP2G00-Q1 Low-Power Dual 2-Input Positive-NAND Gate datasheet		30 Jun 2010
	Application brief	Understanding Schmitt Triggers (Rev. A)	PDF \| HTML	22 Mai 2019
	Selection guide	Little Logic Guide 2018 (Rev. G)		06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)		26 Jul 2016
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004

Design und Entwicklung

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Evaluierungsplatine

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Benutzerhandbuch: PDF

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Simulationsmodell

SN74AUP2G00 Behavioral SPICE Model

SCEM682.ZIP (7 KB) - PSpice Model

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VSSOP (DCU)	8	Optionen anzeigen

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SN74AUP2G00-Q1

2-Kanal, 2 Eingänge, 0,8-V- bis 3,6-V-NAND-Gatter mit geringem Stromverbrauch für die Automobilindus

SN74AUP2G00-Q1

Produktdetails

Technische Dokumentation

Design und Entwicklung

5-8-LOGIC-EVM — Generisches Logik-Evaluierungsmodul für 5- bis 8-polige DCK-, DCT-, DCU-, DRL- und DBV-Gehäuse

SN74AUP2G00 Behavioral SPICE Model

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