Produktdetails

Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Number of channels 8 IOL (max) (mA) 24 IOH (max) (mA) -15 Input type TTL Output type TTL Features High speed (tpd 10-50ns) Technology family LS Rating Catalog Operating temperature range (°C) 0 to 70
Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Number of channels 8 IOL (max) (mA) 24 IOH (max) (mA) -15 Input type TTL Output type TTL Features High speed (tpd 10-50ns) Technology family LS Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Bus Transceivers/Registers
  • Independent Registers and Enables for A and B Buses
  • Multiplexed Real-Time and Stored Data
  • Choice of True and Inverting Data Paths
  • Choice of 3-State or Open-Collector Outputs to A Bus
  • Dependable Texas Instruments Quality and Reliability
  • Bus Transceivers/Registers
  • Independent Registers and Enables for A and B Buses
  • Multiplexed Real-Time and Stored Data
  • Choice of True and Inverting Data Paths
  • Choice of 3-State or Open-Collector Outputs to A Bus
  • Dependable Texas Instruments Quality and Reliability

These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Enable GAB and G\BA are provided to control the transceiver functions. SAB and SBA control pins are provided to select whether realtime or stored data is transferred. A low input level selects real-time data, and a high selects stored data. The following examples demonstrate the four fundamental bus-management functions that can be performed with the 'LS651, 'LS652, and 'LS653.

Data on the A or B data bus, or both, can be stored in the internal D flip-flop by low-to-high transitions at the appropriate clock pins (CAB or CBA) regardless of the select or enable control pins. When SAB or SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and G\BA. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.

The SN54LS651 through SN54LS653 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS651 through SN74LS653 are characterized for operation from 0°C to 70°C.

These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Enable GAB and G\BA are provided to control the transceiver functions. SAB and SBA control pins are provided to select whether realtime or stored data is transferred. A low input level selects real-time data, and a high selects stored data. The following examples demonstrate the four fundamental bus-management functions that can be performed with the 'LS651, 'LS652, and 'LS653.

Data on the A or B data bus, or both, can be stored in the internal D flip-flop by low-to-high transitions at the appropriate clock pins (CAB or CBA) regardless of the select or enable control pins. When SAB or SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and G\BA. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.

The SN54LS651 through SN54LS653 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS651 through SN74LS653 are characterized for operation from 0°C to 70°C.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet Octal Bus Transceivers And Registers datasheet (Rev. A) 11 Dez 2000
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Designing with the SN54/74LS123 (Rev. A) 01 Mär 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996

Design und Entwicklung

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14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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