Inicio Gestión de la energía Circuitos integrados multicanal (PMIC)
Inicio
Gestión de la energía
Circuitos integrados multicanal (PMIC)

LP2998

ACTIVO

Regulador de terminación DDR de 1,5 A con pin de desconexión

Haga su pedido ahora
Hoja de datos

LP2998

ACTIVO
Hoja de datos Haga su pedido ahora

Detalles del producto

Vin (min) (V) 1.35 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Iq (typ) (mA) 0.32 Rating Catalog Operating temperature range (°C) -40 to 125 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L
Vin (min) (V) 1.35 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Iq (typ) (mA) 0.32 Rating Catalog Operating temperature range (°C) -40 to 125 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L
HSOIC (DDA) 8 29.4 mm² 4.9 x 6 SOIC (D) 8 29.4 mm² 4.9 x 6
  • AEC-Q100 Test Guidance with the following results
    (SO PowerPAD-8):
    • Device HBM ESD Classification Level H1C
    • Junction Temperature Range –40°C to 125°C
  • 1.35 V Minimum VDDQ
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • AEC-Q100 Test Guidance with the following results
    (SO PowerPAD-8):
    • Device HBM ESD Classification Level H1C
    • Junction Temperature Range –40°C to 125°C
  • 1.35 V Minimum VDDQ
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown

The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.
open-in-new Buscar otro/a Circuitos integrados multicanal (PMIC)
Descargar Ver vídeo con transcripción Video

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 11
Tipo Título Fecha
* Data sheet LP2998/LP2998-Q1 DDR Termination Regulator datasheet (Rev. K) PDF | HTML 20 ago 2014
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 09 jul 2020
Application note Limiting DDR Termination Regulators’ Inrush Current 23 ago 2016
EVM User's guide AN-1813 LP2998 Evaluation Board (Rev. A) 07 may 2013
Application note AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) 06 may 2013
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 28 abr 2010
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices 20 abr 2010
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) 31 mar 2010
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 26 mar 2010
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs 26 mar 2010
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers 26 mar 2010

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

LP2998EVAL — Placa de evaluación para LP2998

The LP2998 evaluation board is designed to provide the design Engineer with a fully functional prototype system in which to evaluate the LP2998 in both a static environment and with a complete memory system.

Guía del usuario: PDF
No disponible en TI.com
Modelo de simulación

LP2998 PSPICE Transient Model (Rev. B)

SNVM695B.ZIP (48 KB) - PSpice Model
Descargar
Modelo de simulación

LP2998 TINA-TI Transient Reference Design

SNVMB49.TSC (599 KB) - TINA-TI Reference Design
Descargar
Modelo de simulación

LP2998 TINA-TI Transient Spice Model

SNVMB48.ZIP (39 KB) - TINA-TI Spice Model
Descargar
Modelo de simulación

LP2998 Unencrypted PSpice Model

SNVMAF5.ZIP (7 KB) - PSpice Model
Descargar
Diseños de referencia

TIDA-010011 — Diseño de referencia de arquitectura de fuente de alimentación de alta eficiencia para módulo de pro

This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

PMP10600 — Solución de alimentación Xilinx® Zynq®7000 series (XC7Z015), 5 W - Diseño de referencia

The PMP10600.1 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA.   This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator.  It also features one LM3880 for power up and power (...)
Test report: PDF
Esquema: PDF
Diseños de referencia

PMP10601 — Solución de alimentación Xilinx® Zynq® 7000 series (XC7Z015), 8 W - Diseño de referencia

The PMP10601 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015)  FPGA.   This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA.  It also (...)
Test report: PDF
Esquema: PDF
Diseños de referencia

PMP10613 — Diseño de referencia de 20 W de la serie Xilinx Zynq 7000 (XC7Z045)

The PMP10613 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z045)  FPGA.   This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA.  It (...)
Test report: PDF
Esquema: PDF
Diseños de referencia

PMP9766 — Diseño de referencia de fuente de alimentación de reserva de supercondensador con equilibrio de celd

This reference design describes a backup power circuit which addresses instantaneous protection against power interruptions by using a buck-boost converter and two stacked supercapacitors. The implementation is based on a completely integrated TPS63020 buck-boost converter circuit enabling a small (...)
Test report: PDF
Esquema: PDF
Diseños de referencia

PMP10630 — Diseño de referencia de la FPGA Xilinx Kintex UltraScale XCKU040 Power Solution, 6 W

The PMP10630 reference design is a complete high density power solution for Xilinx® Kintex® UltraScale™ XCKU040 FPGA. This design uses an optimal combination of SIMPLE SWITCHER® modules and LDOs to provide all the necessary voltage rails in a small solution size of 36 x 43 mm (1.4 (...)
Test report: PDF
Esquema: PDF
Paquete Pasadores Descargar
HSOIC (DDA) 8 Ver opciones
SOIC (D) 8 Ver opciones
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos