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REF6025

ACTIVO

Referencia de tensión de alta precisión de 2.5 V y 5 ppm/°C con búfer integrado y pin de activación

Detalles del producto

VO (V) 2.5 Initial accuracy (max) (%) 0.05 Temp coeff (max) (ppm/°C) 5 Vin (min) (V) 3 Vin (max) (V) 5.5 Iq (typ) (mA) 0.82 Rating Catalog Features Integrated low-output impedance buffer LFN 0.1 to 10 Hz (typ) (µVPP) 7.5 Iout/Iz (max) (mA) 4 Operating temperature range (°C) -40 to 125 Shutdown current (ISD) (typ) (µA) 1
VO (V) 2.5 Initial accuracy (max) (%) 0.05 Temp coeff (max) (ppm/°C) 5 Vin (min) (V) 3 Vin (max) (V) 5.5 Iq (typ) (mA) 0.82 Rating Catalog Features Integrated low-output impedance buffer LFN 0.1 to 10 Hz (typ) (µVPP) 7.5 Iout/Iz (max) (mA) 4 Operating temperature range (°C) -40 to 125 Shutdown current (ISD) (typ) (µA) 1
VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Excellent Temperature Drift Performance
    • 5 ppm/°C (max) from –40°C to +125°C
  • Extremely Low Noise
    • Total Noise: 5 µVRMS With 47-µF Capacitor
    • 1/f Noise (0.1 Hz to 10 Hz): 3 µVPP/V
  • Integrated ADC Drive Buffer
    • Low Output Impedance: < 50 mΩ (0-200 kHz)
    • First Sample Precise to 18 Bits With ADS8881
    • Enables Burst-Mode DAQ Systems
  • Low Supply Current: 820 µA
  • Low Shutdown Current: 1 µA
  • High Initial Accuracy: ±0.05%
  • Very-Low Noise and Distortion
    • SNR: 100.5 dB, THD: –125 dB (ADS8881)
    • SNR: 106 dB, THD: –120 dB (ADS127L01)
  • Output Current Drive: ±4 mA
  • Programmable Short-Circuit Current
  • Verified to Drive REF Pin of ADS88xx family of SAR ADCs and ADS127xx family of Wideband ΔΣ ADCs
  • Excellent Temperature Drift Performance
    • 5 ppm/°C (max) from –40°C to +125°C
  • Extremely Low Noise
    • Total Noise: 5 µVRMS With 47-µF Capacitor
    • 1/f Noise (0.1 Hz to 10 Hz): 3 µVPP/V
  • Integrated ADC Drive Buffer
    • Low Output Impedance: < 50 mΩ (0-200 kHz)
    • First Sample Precise to 18 Bits With ADS8881
    • Enables Burst-Mode DAQ Systems
  • Low Supply Current: 820 µA
  • Low Shutdown Current: 1 µA
  • High Initial Accuracy: ±0.05%
  • Very-Low Noise and Distortion
    • SNR: 100.5 dB, THD: –125 dB (ADS8881)
    • SNR: 106 dB, THD: –120 dB (ADS127L01)
  • Output Current Drive: ±4 mA
  • Programmable Short-Circuit Current
  • Verified to Drive REF Pin of ADS88xx family of SAR ADCs and ADS127xx family of Wideband ΔΣ ADCs

The REF6000 family of voltage references have an integrated low output impedance buffer that enable the user to directly drive the REF pin of precision data converters, while preserving linearity, distortion, and noise performance. Most precision SAR and Delta-Sigma ADCs, switch binary-weighted capacitors onto the REF pin during the conversion process. In order to support this dynamic load the output of the voltage reference must be buffered with a low-output impedance (high-bandwidth) buffer. The REF6000 family devices are well suited, but not limited, to drive the REF pin of the ADS88xx family of SAR ADCs, and ADS127xx family of delta-sigma ADCs, as well as other digital-to-analog converters (DACs).

The REF6000 family of voltage references are able to maintain an output voltage within 1LSB (18-bit) with minimal droop, even during the first conversion while driving the REF pin of the ADS8881. This feature is useful in burst-mode, event-triggered, equivalent-time sampling, and variable-sampling-rate data-acquisition systems. The REF60xx variants of REF6000 family specify a maximum temperature drift of just 5 ppm/°C and initial accuracy of 0.05% for both the voltage reference and the low output impedance buffer combined. For various temperature drift options in REF6000 family, see the Device Comparison Table.

The REF6000 family of voltage references have an integrated low output impedance buffer that enable the user to directly drive the REF pin of precision data converters, while preserving linearity, distortion, and noise performance. Most precision SAR and Delta-Sigma ADCs, switch binary-weighted capacitors onto the REF pin during the conversion process. In order to support this dynamic load the output of the voltage reference must be buffered with a low-output impedance (high-bandwidth) buffer. The REF6000 family devices are well suited, but not limited, to drive the REF pin of the ADS88xx family of SAR ADCs, and ADS127xx family of delta-sigma ADCs, as well as other digital-to-analog converters (DACs).

The REF6000 family of voltage references are able to maintain an output voltage within 1LSB (18-bit) with minimal droop, even during the first conversion while driving the REF pin of the ADS8881. This feature is useful in burst-mode, event-triggered, equivalent-time sampling, and variable-sampling-rate data-acquisition systems. The REF60xx variants of REF6000 family specify a maximum temperature drift of just 5 ppm/°C and initial accuracy of 0.05% for both the voltage reference and the low output impedance buffer combined. For various temperature drift options in REF6000 family, see the Device Comparison Table.

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Documentación técnica

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Tipo Título Fecha
* Data sheet REF60xx High-Precision Voltage Reference With Integrated ADC Drive Buffer datasheet (Rev. B) PDF | HTML 29 ago 2016
Product overview PLC Analog Input Front-End Architectures PDF | HTML 31 jul 2022
E-book Tips and tricks for designing with voltage references (Rev. A) 07 may 2021
Application note Expanding Analog Input Channels in Grid Applications (Using 16-Channel, 16-Bit, (Rev. A) 26 feb 2021
E-book Voltage Supervisor and Reset ICs: Tips, Tricks and Basics 28 jun 2019
White paper Voltage-reference impact on total harmonic distortion 01 ago 2016
EVM User's guide REF6025EVM-PDK User Guide 19 may 2016

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

ADS127L01EVM — Módulo de evaluación de ADS127L01

The ADS127L01EVM is an evaluation platform for the ADS127L01. The ADS127L01 is a 24-bit, delta-sigma analog-to-digital converter (ADC) with data rates up to 512 kSPS. It offers a unique combination of excellent dc accuracy and outstanding ac perforamnce. The high-order, chopper-stabilized modulator (...)

Guía del usuario: PDF
Placa de evaluación

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The ADS7066 evaluation module (EVM) performance demonstration kit (PDK) is a platform for evaluating the performance of the ADS7066 successive approximation register (SAR) analog-to-digital converter (ADC)

The ADS7066EVM-PDK provides power and a communications card complete with a graphical user (...)

Guía del usuario: PDF
Placa de evaluación

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The ADS8881EVMV2-PDK is an evaluation platform for the ADS8881 successive approximation register (SAR) analog-to-digital converter (ADC). The evaluation kit includes the ADS8881 EVMV2 board, the PHI controller board, and accompanying computer software that enables the user to communicate with (...)
Guía del usuario: PDF
Placa de evaluación

REF6025EVM-PDK — Módulo de evaluación REF6025 de referencia de tensión

The REF6025EVM-PDK is a platform for evaluating the performance of the REF6025 voltage reference. The evaluation kit brings out the burst mode performance of the device which is a key feature of the device.
Guía del usuario: PDF
Modelo de simulación

REF6025 TINA-TI Reference Design

SBOM985.TSC (6483 KB) - TINA-TI Reference Design
Modelo de simulación

REF6025 TINA-TI Transient Spice Model

SBOM984.ZIP (31 KB) - TINA-TI Spice Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Esquema: PDF
Diseños de referencia

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Diseños de referencia

TIPD173 — Diseño de referencia de adquisición de datos de 16 bits y 1 MSPS para aplicaciones multiplexadas de

This TI Precision Verified Design details a systematic design methodology for a 16 bit, 1MSPS, single-ended data acquisition (DAQ) block optimized to achieve excellent settling time, power consumption, static performance and dynamic performance for multiplexed applications.  The design (...)
Design guide: PDF
Esquema: PDF
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VSSOP (DGK) 8 Ver opciones

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  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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