SN74AHCT139

Name: SN74AHCT139
Brand: TI
SKU: SN74AHCT139
Price: 0.164 USD

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Decodificadores/demultiplexores dobles de 2 a 4 líneas

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Hoja de datos

document-pdfAcrobat SN54AHCT139, SN74AHCT139 datasheet (Rev. M) (Inglés)

SN74AHCT139

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Detalles del producto

Technology family

AHCT

Number of channels

2

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Supply current (max) (µA)

20

Technology family

AHCT

Number of channels

2

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Supply current (max) (µA)

20

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SSOP (DB)

16

48.36 mm² 6.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

TVSOP (DGV)

16

23.04 mm² 3.6 x 6.4

Inputs Are TTL-Voltage Compatible
Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Inputs Are TTL-Voltage Compatible
Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

The ’AHCT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V V_CC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

The ’AHCT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V V_CC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

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Documentación técnica

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Ver todo 19

	Tipo	Título	Fecha
*	Data sheet	SN54AHCT139, SN74AHCT139 datasheet (Rev. M)	07 mar 2003
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 jul 2021
	Selection guide	Little Logic Guide 2018 (Rev. G)	06 jul 2018
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	How to Select Little Logic (Rev. A)	26 jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	Product overview	Design Summary for WCSP Little Logic (Rev. B)	04 nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 jun 2004
	Application note	Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)	02 dic 2002
	Application note	Texas Instruments Little Logic Application Report	01 nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 ago 2002
	Design guide	AHC/AHCT Designer's Guide February 2000 (Rev. D)	24 feb 2000
	Product overview	Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)	01 abr 1998
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	01 dic 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 ago 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 jun 1997
	Application note	Live Insertion	01 oct 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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