DS100DF410
- Each Channel Independently Locks to 10.3125 Gbps
- Lock Operation (typically under 15 ms)
- Low Latency (∼300 ps)
- Adaptive Equalization up to 34 dB Boost at 5 GHz
- Adjustable Transmit VOD: 600 to 1300 mVp-p
- Adjustable Transmit De-emphasis to –12 dB
- Typical Power Dissipation (EQ+DFE+CDR+DE): 180 mW/channel
- Programmable Output Polarity Inversion
- Input Signal Detection, CDR Lock Detection/Indicator
- On-chip Eye Monitor (EOM), PRBS Generator
- Single 2.5 V ±5% Power Supply
- SMBus/EEPROM Configuration Modes
- Operating Temperature Range of –40°C to 85°C
- WQFN 48-Pin, 7 mm × 7 mm Package
- Easy Pin Compatible Upgrade Between Repeater and Retimers
- DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
- DS100DF410 (EQ+DFE+CDR+DE): 10.3125 Gbps
- DS110RT410 (EQ+CDR+DE): 8.5–11.3 Gbps
- DS110DF410 (EQ+DFE+CDR+DE): 8.5–11.3 Gbps
- DS125RT410 (EQ+CDR+DE): 9.8–12.5 Gbps
- DS125DF410 (EQ+DFE+CDR+DE): 9.8–12.5 Gbps
- DS100BR410 (EQ+DE): Up to 10.3125 Gbps
The DS100DF410 is four channel retimers with integrated signal conditioning. Each channel can independently lock to 10.3125 Gbps data rate to support 10GbE. The device includes a fully adaptive Continuous-Time Linear Equalizer (CTLE), Clock and Data Recovery (CDR) and transmit De-Emphasis (DE) driver. The DS100DF410 also includes a self calibrating 5-tap Decision Feedback Equalizer (DFE) to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1 × 10–15.
The programmable settings can be applied easily using the SMBus (I2C) interface, or they can be loaded via an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning. Flow-through pinout and single power supply make the DS100DF410 easy to use.
기술 문서
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS100DF410 Low Power 10GbE Quad Channel Retimer datasheet (Rev. B) | PDF | HTML | 2015/01/08 |
| Application note | Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications (Rev. A) | 2023/01/31 | ||
| Application note | Implementing TI Retimers on 10G ZR and DWDM SFP+ Optical Links | 2019/04/08 | ||
| Application brief | DS110DF111,DS125DF111, DS100DF410, DS110DF410, and DS125DF410 Programming Guide | 2019/03/25 | ||
| EVM User's guide | DS100DF410EVK, DS110DF410EVK, DS125DF410EVM User's Guide (Rev. C) | 2016/06/22 | ||
| Application note | Understanding EEPROM Programming for 10G to 12.5G Retimers | 2016/01/13 | ||
| Application note | Selecting TI SigCon Devices for SFF-8431 SFP+ Applications | 2014/05/06 |
설계 및 개발
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DS100DF410EVK — DS100DF410EVK 평가 보드
The DS100DF410EVK evaluation board allows the user to examine the advanced signal conditioning capabilities of the DS100DF410 and DS100RT410 devices using SMAs. The board is controlled by a PC using a USB port and the SigCon Architect GUI.
In order to use the SigCon Architect GUI to control the (...)
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
| 패키지 | 핀 | 다운로드 |
|---|---|---|
| WQFN (RHS) | 48 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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