SN74ACT7803

Name: SN74ACT7803
Brand: TI
SKU: SN74ACT7803
Price: 18.043 USD

활성

512 x 18 동기 FIFO 메모리

지금 주문

데이터시트

document-pdfAcrobat 512 X 18 Clocked First-In, First-Out Memory datasheet (Rev. C) (영어)

SN74ACT7803

활성

데이터시트

지금 주문

제품 상세 정보

Technology family

ACT

Rating

Military

Operating temperature range (°C)

0 to 70

Technology family

ACT

Rating

Military

Operating temperature range (°C)

0 to 70

SSOP (DL)

56

190.647 mm² 18.42 x 10.35

Member of the Texas Instruments Widebus^TM Family
Free-Running Read and Write Clocks Can Be Asynchronous or Coincident
Read and Write Operations Synchronized to Independent System Clocks
Input-Ready Flag Synchronized to Write Clock
Output-Ready Flag Synchronized to Read Clock
512 Words by 18 Bits
Low-Power Advanced CMOS Technology
Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag
Bidirectional Configuration and Width Expansion Without Additional Logic
Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
Data Rates up to 67 MHz
Pin-to-Pin Compatible With SN74ACT7805 and SN74ACT7813
Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing
Widebus and OEC are trademarks of Texas Instruments Incorporated.

Member of the Texas Instruments Widebus^TM Family
Free-Running Read and Write Clocks Can Be Asynchronous or Coincident
Read and Write Operations Synchronized to Independent System Clocks
Input-Ready Flag Synchronized to Write Clock
Output-Ready Flag Synchronized to Read Clock
512 Words by 18 Bits
Low-Power Advanced CMOS Technology
Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag
Bidirectional Configuration and Width Expansion Without Additional Logic
Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
Data Rates up to 67 MHz
Pin-to-Pin Compatible With SN74ACT7805 and SN74ACT7813
Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing
Widebus and OEC are trademarks of Texas Instruments Incorporated.

The SN74ACT7803 is a 512-word × 18-bit FIFO suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed V_CC and GND pins, along with Texas Instruments patented output edge control (OEC^TM) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.

The SN74ACT7803 is characterized for operation from 0°C to 70°C.

The SN74ACT7803 is a 512-word × 18-bit FIFO suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed V_CC and GND pins, along with Texas Instruments patented output edge control (OEC^TM) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.

The SN74ACT7803 is characterized for operation from 0°C to 70°C.

open-in-new

기타 전문 로직 IC 찾기

다운로드 스크립트와 함께 비디오 보기 동영상

기술 문서

star

=TI에서 선정한 이 제품의 인기 문서

검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.

모두 보기14

	유형	직함	날짜
*	Data sheet	512 X 18 Clocked First-In, First-Out Memory datasheet (Rev. C)	1998/04/01
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	2021/07/26
	Selection guide	Logic Guide (Rev. AB)	2017/06/12
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	2015/12/02
	User guide	LOGIC Pocket Data Book (Rev. B)	2007/01/16
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	2004/07/08
	Application note	Selecting the Right Level Translation Solution (Rev. A)	2004/06/22
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	2002/08/29
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	1997/06/01
	Application note	Designing With Logic (Rev. C)	1997/06/01
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc	1996/04/01
	Application note	FIFO Memories: Solutions For Increasing Clock Rates And Data Widths (Rev. A)	1996/03/01
	Application note	Power-Dissipation Calculations for TI FIFO Products (Rev. A)	1996/03/01
	Application note	Simultaneous-Switching Noise Analysis For Texas Instruments FIFO Products (Rev. A)	1996/03/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

패키지	핀	다운로드
SSOP (DL)	56	옵션 보기

TI의 평가 항목에 대한 표준 약관이 적용됩니다.

SN74ACT7803

512 x 18 동기 FIFO 메모리

SN74ACT7803

제품 상세 정보

기술 문서

설계 및 개발

주문 및 품질

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

비디오 시리즈

동영상