SN74LV4T125

활성

3상 출력 CMOS 로직 레벨 시프터를 지원하는 단일 전원 공급 쿼드러플 버퍼 게이트

제품 상세 정보

Technology family LV-A Applications SPI Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 19 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -16 IOL (max) (mA) -16 Supply current (max) (µA) 5.5 Features 12.25, 32 Input type TTL-Compatible CMOS Output type 3-State, Balanced CMOS Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-A Applications SPI Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 19 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -16 IOL (max) (mA) -16 Supply current (max) (µA) 5.5 Features 12.25, 32 Input type TTL-Compatible CMOS Output type 3-State, Balanced CMOS Rating Catalog Operating temperature range (°C) -40 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5
  • Single-Supply Voltage Translator at 5.0-V, 3.3-V, 2.5-V, and 1.8-V VCC
  • Operating Range of 1.8 V to 5.5 V
  • Up Translation
    • 1.2 V(1) to 1.8 V at 1.8-V VCC
    • 1.5 V(1) to 2.5 V at 2.5-V VCC
    • 1.8 V(1) to 3.3 V at 3.3-V VCC
    • 3.3 V to 5.0 V at 5.0-V VCC
  • Down Translation
    • 3.3 V to 1.8 V at 1.8-V VCC
    • 3.3 V to 2.5 V at 2.5-V VCC
    • 5.0 V to 3.3 V at 3.3-V VCC
  • Logic Output is Referenced to VCC
  • Characterized up to 50 MHz at 3.3-V VCC
  • 5.5 V Tolerance on Input Pins
  • –40°C to 125°C Operating Temperature Range
  • Pb-Free Packages Available: SC-70 (RGY)
    • 3.5 × 3.5 × 1 mm
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Supports Standard Logic Pinouts
  • Ioff Support Partial-Power-Down Mode Operation
  • CMOS Output B Compatible with AUP125, LVC125 (1)

(1)Refer the VIH/VIL and output drive for lower VCC condition.

  • Single-Supply Voltage Translator at 5.0-V, 3.3-V, 2.5-V, and 1.8-V VCC
  • Operating Range of 1.8 V to 5.5 V
  • Up Translation
    • 1.2 V(1) to 1.8 V at 1.8-V VCC
    • 1.5 V(1) to 2.5 V at 2.5-V VCC
    • 1.8 V(1) to 3.3 V at 3.3-V VCC
    • 3.3 V to 5.0 V at 5.0-V VCC
  • Down Translation
    • 3.3 V to 1.8 V at 1.8-V VCC
    • 3.3 V to 2.5 V at 2.5-V VCC
    • 5.0 V to 3.3 V at 3.3-V VCC
  • Logic Output is Referenced to VCC
  • Characterized up to 50 MHz at 3.3-V VCC
  • 5.5 V Tolerance on Input Pins
  • –40°C to 125°C Operating Temperature Range
  • Pb-Free Packages Available: SC-70 (RGY)
    • 3.5 × 3.5 × 1 mm
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Supports Standard Logic Pinouts
  • Ioff Support Partial-Power-Down Mode Operation
  • CMOS Output B Compatible with AUP125, LVC125 (1)

(1)Refer the VIH/VIL and output drive for lower VCC condition.

SN74LV4T125 is a low-voltage CMOS buffer gate that operates at a wider voltage range for portable, telecom, industrial, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to match 1.8-V input logic at VCC = 3.3 V and can be used in 1.8 V to 3.3 V level-up translation. In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output at VCC = 2.5 V). The wide VCC range of 1.8 V to 5.5 V allows the generation of desired output levels to connect to controllers or processors.

The SN74LV4T125 device is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

SN74LV4T125 is a low-voltage CMOS buffer gate that operates at a wider voltage range for portable, telecom, industrial, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to match 1.8-V input logic at VCC = 3.3 V and can be used in 1.8 V to 3.3 V level-up translation. In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output at VCC = 2.5 V). The wide VCC range of 1.8 V to 5.5 V allows the generation of desired output levels to connect to controllers or processors.

The SN74LV4T125 device is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new 대안 비교
다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능
SN74LV8T245 활성 3상 출력을 지원하는 단일 공급 8진 변환 트랜시버 Single-supply version of 8-bit fixed direction translator

기술 문서

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모두 보기6
유형 직함 날짜
* Data sheet SN74LV4T125 Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter datasheet (Rev. C) PDF | HTML 2022/06/14
Application brief Enabling Modular PLC System Designs with Single-Supply Level Translation PDF | HTML 2024/04/16
Selection guide Voltage Translation Buying Guide (Rev. A) 2021/04/15
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015/04/30
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML
TI.com에서 구매할 수 없습니다
평가 보드

14-24-NL-LOGIC-EVM — 14핀~24핀 비 리드 패키지용 로직 제품 일반 평가 모듈

14-24-NL-LOGIC-EVM은 14핀~24핀 BQA, BQB, RGY, RSV, RJW 또는 RHL 패키지가 있는 로직 또는 변환 디바이스를 지원하도록 설계된 유연한 평가 모듈(EVM)입니다.

사용 설명서: PDF | HTML
TI.com에서 구매할 수 없습니다
시뮬레이션 모델

SN74LV4T125 IBIS Model

SCLM112.ZIP (50 KB) - IBIS Model
레퍼런스 디자인

TIDA-01373 — EEPROM 프로그래밍 툴 레퍼런스 디자인

The TIDA-01373 is a reference hardware and software example of a scalable programming tool for the DRV10983, DRV10975, DRV10983-Q1, and DRV10987 integrated BLDC motor drivers. These devices feature configurable EEPROM registers that need to be set to motor-specific parameters. This reference (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDA-01370 — 스톨 감지를 위한 인코더를 갖춘 폐쇄형 루프 스테퍼 모터 레퍼런스 디자인

This reference design is used for the stall-detection in a stepper motor driven by DRV8880 in the presence of a closed-loop feedback obtained with an optical rotary incremental encoder.  The reference design shows how to detect a stall using a closed-loop algorithm.
Design guide: PDF
회로도: PDF
패키지 다운로드
TSSOP (PW) 14 옵션 보기
VQFN (RGY) 14 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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