홈 로직 및 전압 변환 버퍼, 드라이버 및 트랜시버 범용 트랜시버
홈
로직 및 전압 변환
버퍼, 드라이버 및 트랜시버
범용 트랜시버

SN74LVTH16543

활성

3상 출력을 지원하는 3.3V ABT 16비트 레지스터 트랜시버

지금 주문
데이터시트

SN74LVTH16543

활성
데이터시트 지금 주문

제품 상세 정보

Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 64 IOH (max) (mA) -64 Input type TTL/CMOS Output type LVTTL Features Balanced outputs Technology family LVT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 64 IOH (max) (mA) -64 Input type TTL/CMOS Output type LVTTL Features Balanced outputs Technology family LVT Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm² 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

Widebus is a trademark of Texas Instruments Incorporated.
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

Widebus is a trademark of Texas Instruments Incorporated.

The 'LVTH16543 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB\) input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA\, LEBA\, and OEBA\ inputs.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN54LVTH16543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16543 is characterized for operation from -40°C to 85°C.

The 'LVTH16543 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB\) input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA\, LEBA\, and OEBA\ inputs.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN54LVTH16543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16543 is characterized for operation from -40°C to 85°C.

open-in-new 기타 범용 트랜시버 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
74ACT16245 활성 3상 출력을 지원하는 16비트 버스 트랜시버 Voltage range (4.5V to 5.5V)
비교 대상 장치와 유사한 기능
SN74ACT245 활성 TTL 호환 CMOS 입력 및 3상 출력을 지원하는 옥탈 버스 트랜시버 Voltage range (4.5V to 5.5V)

기술 문서

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
모두 보기17
유형 직함 날짜
* Data sheet 3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputs datasheet (Rev. D) 1999/04/07
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018/09/17
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
Selection guide Advanced Bus Interface Logic Selection Guide 2001/01/09
Application note LVT-to-LVTH Conversion 1998/12/08
Application note LVT Family Characteristics (Rev. A) 1998/03/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 모델

SN74LVTH16543 IBIS Model

SCBM073.ZIP (20 KB) - IBIS Model
다운로드
패키지 핀 다운로드
SSOP (DL) 56 옵션 보기
TSSOP (DGG) 56 옵션 보기
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상