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TLK10232

활성

크로스포인트 스위치를 지원하는 듀얼 채널 XAUI-to-10GBASE-KR 백플레인 트랜시버

제품 상세 정보

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
FCBGA (CTR) 144 169 mm² 13 x 13
  • Dual Channel Multi-Rate Transceiver
  • Supports 10GBASE-KR, XAUI, and 1GBASE-KX Ethernet
    Standards
  • Supports all CPRI and OBSAI Data Rates up to 10 Gbps
  • Supports Multi-Rate SERDES Operation with up to 10.3125
    Gbps Data Rate on the High Speed Side and up to 5 Gbps
    on the Low Speed Side
  • Differential CML I/Os on Both High Speed and Low Speed Sides
  • Interface to Backplanes, Passive and Active Copper Cables,
    or SFP+ Optical Modules
  • Selectable Reference Clock per Channel with Multiple
    Output Clock Options
  • Integrated Crosspoint Switch Allows for Flexible Signal
    Routing and Redundant Outputs
  • Supports Data Retime Operation
  • Supports PRBS, CRPAT, CJPAT, High/Low/Mixed-Frequency
    Patterns, and KR Pseudo-Random Pattern Generation and
    Verification, Square-Wave Generation
  • Two Power Supplies: 1.0V (Core), and 1.5 or 1.8V (I/O)
  • No Power Supply Sequencing Requirements
  • Transmit De-emphasis and Receive Adaptive Equalization
    to Allow Extended Backplane/Cable Reach on Both High
    Speed and Low Speed Sides
  • Loss of Signal (LOS) Detection
  • Supports 10G-KR Link Training, Forward Error Correction,
    Auto-Negotiation
  • Jumbo Packet Support
  • JTAG; IEEE 1149.1 Test Interface
  • Industry Standard MDIO Control Interface
  • 65nm Advanced CMOS Technology
  • Industrial Ambient Operating Temperature
    (–40°C to 85°C)
  • Power Consumption: 800mW per Channel (Nominal)
  • Device Package: 13mm × 13mm, 144-pin PBGA,
    1-mm Ball-Pitch
  • Dual Channel Multi-Rate Transceiver
  • Supports 10GBASE-KR, XAUI, and 1GBASE-KX Ethernet
    Standards
  • Supports all CPRI and OBSAI Data Rates up to 10 Gbps
  • Supports Multi-Rate SERDES Operation with up to 10.3125
    Gbps Data Rate on the High Speed Side and up to 5 Gbps
    on the Low Speed Side
  • Differential CML I/Os on Both High Speed and Low Speed Sides
  • Interface to Backplanes, Passive and Active Copper Cables,
    or SFP+ Optical Modules
  • Selectable Reference Clock per Channel with Multiple
    Output Clock Options
  • Integrated Crosspoint Switch Allows for Flexible Signal
    Routing and Redundant Outputs
  • Supports Data Retime Operation
  • Supports PRBS, CRPAT, CJPAT, High/Low/Mixed-Frequency
    Patterns, and KR Pseudo-Random Pattern Generation and
    Verification, Square-Wave Generation
  • Two Power Supplies: 1.0V (Core), and 1.5 or 1.8V (I/O)
  • No Power Supply Sequencing Requirements
  • Transmit De-emphasis and Receive Adaptive Equalization
    to Allow Extended Backplane/Cable Reach on Both High
    Speed and Low Speed Sides
  • Loss of Signal (LOS) Detection
  • Supports 10G-KR Link Training, Forward Error Correction,
    Auto-Negotiation
  • Jumbo Packet Support
  • JTAG; IEEE 1149.1 Test Interface
  • Industry Standard MDIO Control Interface
  • 65nm Advanced CMOS Technology
  • Industrial Ambient Operating Temperature
    (–40°C to 85°C)
  • Power Consumption: 800mW per Channel (Nominal)
  • Device Package: 13mm × 13mm, 144-pin PBGA,
    1-mm Ball-Pitch

The TLK10232 is a dual-channel multi-rate transceiver intended for use in high-speed bi-directional point-to-point data transmission systems. This device supports three primary modes. It can be used as a XAUI to 10GBASE-KR transceiver, as a general-purpose 8b/10b multi-rate 4:1, 2:1, or 1:1 serializer/deserializer, or can be used in 1G-KX mode.

While operating in the 10GBASE-KR mode, the TLK10232 performs serialization of the 8B/10B encoded XAUI data stream presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs in 64B/66B encoding format. Likewise, the TLK10232 performs deserialization of 64B/66B encoded data streams presented on its high speed side data inputs. The deserialized 64B/66B data is presented in XAUI 8B/10B format on the low speed side outputs. Link Training is supported in this mode as well as Forward Error Correction (FEC) for extended length applications.

While operating in the General Purpose SERDES mode, the TLK10232 performs 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10232 performs 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range from 0.5 Gbps to 5 Gbps and the high speed side data rate can range from 1 Gbps to 10 Gbps. 1:1 retime mode is also supported but limited to 1 Gbps to 5 Gbps rates.

The TLK10232 also supports 1G-KX (1.25 Gbps) mode with PCS (CTC) capabilities. This mode can be enabled via software provisioning or via auto negotiation. If software provisioning is used, data rates up to 3.125 Gbps are supported.

The TLK10232 features a built-in crosspoint switch, allowing for redundant outputs and easy re-routing of data. Each output port (either high speed or low speed) can be configured to output data coming from any of the device’s input ports. The switching can be initiated through either a hardware pin or through software control, and can be configured to occur either immediately or after the end of the current packet. This allows for switching between data sources without packet corruption.

Both low speed and high speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors.

The TLK10232 provides flexible clocking schemes to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high speed side. The device is also capable of performing clock tolerance compensation (CTC) in 10GBASE-KR and 1GBASE-KX modes, allowing for asynchronous clocking.

The TLK10232 provides low speed side and high speed side loopback modes for self-test and system diagnostic purposes.

The TLK10232 has built-in pattern generators and verifiers to help in system tests. The device supports generation and verification of various PRBS, High-/Low-/Mixed-Frequency, CRPAT long/short, CJPAT, and KR pseudo-random test patterns and square wave generation. The types of patterns supported on the low speed and high speed side are dependent on the operational mode chosen.

The TLK10232 has an integrated loss of signal (LOS) detection function on both high speed and low speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold.

Both TLK10232 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization/deserialization ratios.

The low speed side of the TLK10232 is ideal for interfacing with an FPGA, ASIC, MAC, or network processor capable of handling lower-rate serial data streams. The high speed side is ideal for interfacing with remote systems through optical fibers, electrical cables, or backplane interfaces. The TLK10232 supports operation with SFP and SFP+ optical modules, as well as 10GBASE-KR compatible backplane systems.

The TLK10232 is a dual-channel multi-rate transceiver intended for use in high-speed bi-directional point-to-point data transmission systems. This device supports three primary modes. It can be used as a XAUI to 10GBASE-KR transceiver, as a general-purpose 8b/10b multi-rate 4:1, 2:1, or 1:1 serializer/deserializer, or can be used in 1G-KX mode.

While operating in the 10GBASE-KR mode, the TLK10232 performs serialization of the 8B/10B encoded XAUI data stream presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs in 64B/66B encoding format. Likewise, the TLK10232 performs deserialization of 64B/66B encoded data streams presented on its high speed side data inputs. The deserialized 64B/66B data is presented in XAUI 8B/10B format on the low speed side outputs. Link Training is supported in this mode as well as Forward Error Correction (FEC) for extended length applications.

While operating in the General Purpose SERDES mode, the TLK10232 performs 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10232 performs 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range from 0.5 Gbps to 5 Gbps and the high speed side data rate can range from 1 Gbps to 10 Gbps. 1:1 retime mode is also supported but limited to 1 Gbps to 5 Gbps rates.

The TLK10232 also supports 1G-KX (1.25 Gbps) mode with PCS (CTC) capabilities. This mode can be enabled via software provisioning or via auto negotiation. If software provisioning is used, data rates up to 3.125 Gbps are supported.

The TLK10232 features a built-in crosspoint switch, allowing for redundant outputs and easy re-routing of data. Each output port (either high speed or low speed) can be configured to output data coming from any of the device’s input ports. The switching can be initiated through either a hardware pin or through software control, and can be configured to occur either immediately or after the end of the current packet. This allows for switching between data sources without packet corruption.

Both low speed and high speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors.

The TLK10232 provides flexible clocking schemes to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high speed side. The device is also capable of performing clock tolerance compensation (CTC) in 10GBASE-KR and 1GBASE-KX modes, allowing for asynchronous clocking.

The TLK10232 provides low speed side and high speed side loopback modes for self-test and system diagnostic purposes.

The TLK10232 has built-in pattern generators and verifiers to help in system tests. The device supports generation and verification of various PRBS, High-/Low-/Mixed-Frequency, CRPAT long/short, CJPAT, and KR pseudo-random test patterns and square wave generation. The types of patterns supported on the low speed and high speed side are dependent on the operational mode chosen.

The TLK10232 has an integrated loss of signal (LOS) detection function on both high speed and low speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold.

Both TLK10232 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization/deserialization ratios.

The low speed side of the TLK10232 is ideal for interfacing with an FPGA, ASIC, MAC, or network processor capable of handling lower-rate serial data streams. The high speed side is ideal for interfacing with remote systems through optical fibers, electrical cables, or backplane interfaces. The TLK10232 supports operation with SFP and SFP+ optical modules, as well as 10GBASE-KR compatible backplane systems.

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기술 문서

star =TI에서 선정한 이 제품의 인기 문서
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모두 보기4
유형 직함 날짜
* Data sheet Dual-Channel XAUI/10GBASE-KR Transceiver with Crosspoint datasheet 2013/05/31
Application note 10GBASE-KR Link Optimization with TLK10034 and TLK10232 (Rev. A) 2019/03/14
User guide TLK10232 EVM GUI User's Guide 2013/03/07
EVM User's guide TLK10232 EVM User's Guide 2013/03/07

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

TLK10232EVM — TLK10232EVM - TLK10232용 마더보드 평가 모듈

Motherboard evaluation board for TLK10232 comes with custom-developed GUI and a detailed EVM user guide. This EVM along with the GUI, enable customers to configure the registers of all the channels independently and to debug the device. The user’s guide provides guidance on proper use of the (...)
사용 설명서: PDF
TI.com에서 구매할 수 없습니다
도터 카드

TLK10XXXSMAEVM — TLK10XXXSMAEVM - TLK10232용 SMA 브레이크아웃 부속 보드

The TLK10XXXSMAEVM SMA breakout daughterboard is used to for evaluation of the low-speed signals on the TLK10232EVM. SMA cables can be connected from the input signals to the output signals to create an external loopback situation, or to standard lab test equipment. The pinout is compatible with (...)

사용 설명서: PDF
TI.com에서 구매할 수 없습니다
평가 모듈(EVM)용 GUI

SLLC435 TLK10232 EVM GUI Software

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
기타 인터페이스
TLK10232 크로스포인트 스위치를 지원하는 듀얼 채널 XAUI-to-10GBASE-KR 백플레인 트랜시버
하드웨어 개발
평가 보드
TLK10232EVM TLK10232EVM - TLK10232용 마더보드 평가 모듈
시뮬레이션 모델

TLK10232 HSPICE Model

SLLM212.ZIP (9166 KB) - HSpice Model
시뮬레이션 모델

TLK10232 IBIS Model

SLLM213.ZIP (60 KB) - IBIS Model
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
레퍼런스 디자인

TIDA-00234 — 2개 이상의 SFP+ 광학 포트가 있는 시스템을 위한 듀얼 채널 XAUI-SFI 레퍼런스 디자인

The TIDA-00234 XAUI to SFI reference design is intended for Enterprise and Service Provider Networking applications like Ethernet Switches and Routers that implement multiple 10G Ethernet compliant Optical (SFP+) ports. This reference design features the TLK10232 device which is the most compact (...)
Test report: PDF
회로도: PDF
패키지 다운로드
FCBGA (CTR) 144 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

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