CDCVF2505-Q1

Name: CDCVF2505-Q1
Brand: TI
SKU: CDCVF2505-Q1
Price: 1.493 USD

不推薦在新設計中採用

車用 PLL 時脈驅動器，適用同步、DRAM 和具展頻壓縮的通用應用

立即訂購

產品規格表

document-pdfAcrobat 3.3-V Clock Phase-Locked Loop Clock Driver datasheet (英文)

CDCVF2505-Q1 不建議用於新設計

儘管為了支援以前的設計而繼續生產此項產品，但我們並不建議用在新設計上。考量下列其中一項替代產品：

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CDCVF2505

現行

用於同步的 PLL 時鐘驅動器DRAM 與 gen. purp. 應用，具備展頻相容性、關閉電源模式 Can achieve better performance

CDCVF2505-Q1

不推薦在新設計中採用

產品規格表

立即訂購

產品詳細資料

Function

Memory interface

Additive RMS jitter (typ) (fs)

70

Output frequency (max) (MHz)

200

Number of outputs

4

Output supply voltage (V)

3.3

Core supply voltage (V)

3.3

Output skew (ps)

150

Operating temperature range (°C)

-40 to 85

Rating

Automotive

Function

Memory interface

Additive RMS jitter (typ) (fs)

70

Output frequency (max) (MHz)

200

Number of outputs

4

Output supply voltage (V)

3.3

Core supply voltage (V)

3.3

Output skew (ps)

150

Operating temperature range (°C)

-40 to 85

Rating

Automotive

SOIC (D)

8

29.4 mm² 4.9 x 6

Qualified for Automotive Applications
Phase-Locked Loop Clock Driver for Synchronous DRAM
and General-Purpose Applications
Spread-Spectrum Clock Compatible
Operating Frequency: 24 MHz to 200 MHz
Low Jitter (Cycle-to-Cycle): <150 ps Over the
Range 66 MHz to 200 MHz
Distributes One Clock Input to One Bank of Five Outputs
(CLKOUT Is Used to Tune the Input-Output Delay)
Three-States Outputs When There Is No Input Clock
Operates From Single 3.3-V Supply
Available in 8-Pin SOIC Package
Consumes Less Than 100 µA (Typically) in
Power Down Mode
Internal Feedback Loop Is Used to Synchronize the
Outputs to the Input Clock
25- On-Chip Series Damping Resistors
Integrated RC PLL Loop Filter Eliminates the
Need for External Components

Qualified for Automotive Applications
Phase-Locked Loop Clock Driver for Synchronous DRAM
and General-Purpose Applications
Spread-Spectrum Clock Compatible
Operating Frequency: 24 MHz to 200 MHz
Low Jitter (Cycle-to-Cycle): <150 ps Over the
Range 66 MHz to 200 MHz
Distributes One Clock Input to One Bank of Five Outputs
(CLKOUT Is Used to Tune the Input-Output Delay)
Three-States Outputs When There Is No Input Clock
Operates From Single 3.3-V Supply
Available in 8-Pin SOIC Package
Consumes Less Than 100 µA (Typically) in
Power Down Mode
Internal Feedback Loop Is Used to Synchronize the
Outputs to the Input Clock
25- On-Chip Series Damping Resistors
Integrated RC PLL Loop Filter Eliminates the
Need for External Components

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN.

Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost.

Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.

The CDCVF2505 is characterized for operation from –40°C to 85°C.

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN.

Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost.

Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.

The CDCVF2505 is characterized for operation from –40°C to 85°C.

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	類型	標題		日期
*	Data sheet	3.3-V Clock Phase-Locked Loop Clock Driver datasheet		2008年 11月 21日

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CDCVF2505-Q1

車用 PLL 時脈驅動器，適用同步、DRAM 和具展頻壓縮的通用應用

功能相似於所比較的產品

CDCVF2505-Q1

產品詳細資料

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