DP83816
- IEEE 802.3 Compliant, PCI V2.2 Media Access
Controller (MAC) and Bus Interface Unit (BIU)
Supports Traditional Data Rates of 10 Mb/s
Ethernet and 100 Mb/s Fast Ethernet (Through
Internal PHY) - Bus Master – Burst Sizes of up to 128 Dwords
(512 Bytes) - BIU Compliant With PC 97 and PC 98 Hardware
Design Guides, PC 99 Hardware Design Guide
Draft, ACPI v1.0, PCI Power Management
Specification v1.1, OnNow Device Class Power
Management Reference Specification – Network
Device Class v1.0a - Wake on LAN (WoL) Support Compliant With
PC98, PC99, SecureOn, and OnNow, Including
Directed Packets, Magic Packet™ VLAN Packets,
ARP Packets, Pattern Match Packets, and PHY
Status Change - Clkrun Function for PCI Mobile Design Guide
- Virtual LAN (VLAN) and Long Frame Support
- Support for IEEE 802.3× Full-Duplex Flow Control
- Extremely Flexible Rx Packet Filtration Including:
Single Address Perfect Filter With MSb Masking,
Broadcast, 512 Entry Multicast and Unicast Hash
Table, Deep Packet Pattern Matching for up to
Four Unique Patterns - Statistics Gathered for Support of RFC 1213
(MIB II), RFC 1398 (Ether-Like MIB), IEEE 802.3
LME, Reducing CPU Overhead for Management - Internal 2KB Transmit and 2KB Receive Data
FIFOs - Serial EEPROM Port With Auto-Load of
Configuration Data From EEPROM at Power On - Flash or PROM Interface for Remote Boot Support
- Fully Integrated IEEE 802.3 3.3-V CMOS Physical
Layer - IEEE 802.3 10BASE-T Transceiver With Integrated
Filters IEEE 802.3u 100BASE-TX Transceiver - Fully integrated ANSI X3.263 Compliant TP-PMD
Physical Sublayer With Adaptive Equalization and
Baseline Wander Compensation - IEEE 802.3u Auto-Negotiation – Advertised
Features Configurable Through EEPROM - Full-Duplex Support for 10- and 100-Mb/s Data
Rates - Single 25-MHz Reference Clock
- 144-pin LQFP Package
- Low-Power 3.3-V CMOS Design With Typical
Consumption of 383 mW Operating, 297 mW
During WoL, and 53 mW During Sleep Mode - IEEE 802.3u MII for Connecting Alternative
External Physical Layer Devices - 3.3-V Signaling With 5-V Tolerant I/O
The DP83816 device is a single-chip 10/100 Mb/s ethernet controller for the PCI bus. It is targeted at low-cost, high-volume PC motherboards, adapter cards, and embedded systems. The DP83816 device fully implements the V2.2 33-MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83816 device can support full-duplex 10/100 Mb/s transmission and reception with minimum interframe gap.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | Integrated PCI Ethernet Media Access Contrlr & Phy Layer (MacPhyter-II) datasheet (Rev. E) | 2015年 12月 31日 | |
User guide | DP83816-MAAP User Guide | 2012年 2月 23日 | ||
Application note | AN-1351 MAC Address Programming for DP83816 MacPHYTER-II and DP83815 MacPHYTER | 2005年 1月 5日 | ||
Application note | AN-1287 DP83815 MacPHYTER and DP83816 MacPHYTER-II High Data Rate Stress Testing | 2004年 5月 1日 | ||
Application note | AN-1323 Updating DP83815 MacPHYTER Hardware Designs to DP83816 MacPHYTER-II | 2004年 5月 1日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
ETHERNET-SW — 乙太網路 PHY Linux 驅動程式和工具
USB-2-MDIO 軟體可讓您在偵錯和原型設計期間直接存取暫存器。 此工具支援所有 TI 乙太網路 PHY。
啓用驅動程式支援
使用 "make menuconfig" 配置核心 (或者使用 "make xconfig" 或 "make nconfig")
Menuconfig 位置
//在下例中更改符號欄位以和零件編號
符號相符:DP83848_PHY [=y]
類型:tristate
提示:適用於德州儀器 DP83848 PHY
(...)
USB-2-MDIO — USB-2-MDIO Tool v1.0
The USB-2-MDIO software tool lets Texas Instruments' Ethernet PHYs access the MDIO status and device control registers. The USB-2-MDIO tool includes a LaunchPad™ Development kit for TI's MSP430™ MCUs that is interfaced with a lightweight GUI. The (...)
支援產品和硬體
產品
乙太網路 PHY
硬體開發
開發板
開發套件
軟體
驅動程式或資料庫
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 引腳 | 下載 |
---|---|---|
LQFP (PGE) | 144 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點