DS90CR286A
- 20 to 66 MHz Shift Clock Support
- 50% Duty Cycle on Receiver Output Clock
- Best–in–Class Set and Hold Times on Rx Outputs
- Rx Power Consumption < 270 mW (Typ) at 66
MHz Worst Case - Rx Power-Down Mode < 200 µW (Max)
- ESD Rating > 7 kV (HBM), > 700 V (EIAJ)
- PLL Requires No External Components
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 56-Pin or 48-Pin DGG (TSSOP)
Package - Operating Temperature: −40°C to 85°C
- Automotive Q Grade Available – AEC-Q100 Grade
3 Qualified
The DS90CR286A receiver converts the four LVDS data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CR216A receiver that converts the three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the rising edge.
The receiver LVDS clock operates at rates from 20 to 66 MHz. The device phase-locks to the input clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps for the DS90CR286A and 1.386 Gbps for the DS90CR216A.
The DS90CR286A and DS90CR216A devices are enhanced over prior generation receivers and provide a wider data valid time on the receiver output. The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz datasheet (Rev. H) | PDF | HTML | 2016年 1月 18日 |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018年 11月 9日 | ||
| Application note | AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) | 2018年 8月 3日 | ||
| Application note | Receiver Skew Margin for Channel Link I and FPD Link I Devices | 2016年 1月 13日 | ||
| Design guide | Channel Link I Design Guide | 2007年 3月 29日 | ||
| Application note | Multi-Drop Channel-Link Operation | 2004年 10月 4日 | ||
| Application note | CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications | 1998年 10月 5日 |
設計與開發
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The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.
The transmitter board accepts (...)
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| 封裝 | 引腳 | 下載 |
|---|---|---|
| TSSOP (DGG) | 56 | 檢視選項 |
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