LMK5C33414A
- Ultra-low jitter BAW VCO based Wireless clocks
- 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz
- 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz
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Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)
- Programmable DPLL loop bandwidth from 1 mHz to 4 kHz
- < 1-ppt DCO frequency adjustment step size
- Four differential or single-ended DPLL inputs
- 1-Hz (1-PPS) to 800-MHz input frequency
- Digital holdover and hitless switching
- 14 differential outputs with programmable HSDS/LVPECL, LVDS and HSCL output formats
- Up to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2 and 12 differential outputs
- 1-Hz (1-PPS) to 1250-MHz output frequency with programmable swing and common mode
- PCIe Gen 1 to 6 compliant
- I 2C, 3-wire SPI, or 4-wire SPI interface
- Ambient operating temperature: –40°C to 85°C
The LMK5C33414A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.
The network synchronizer integrates three DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input.
APLL3 features ultra high performance PLL with TIs proprietary Bulk Acoustic Wave (BAW) technology and can generate 491.52-MHz output clocks with 42-fs typical / 60-fs maximum RMS jitter irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 provide options for a second or third frequency and/or synchronization domain.
Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between them upon detecting a switchover event. Zero-Delay Mode (ZDM) and phase cancellation may be enabled to control the phase relationship from input to outputs.
The device is fully programmable through I 2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.
技術文件
類型 | 標題 | 日期 | ||
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* | Data sheet | LMK5C33414ANetwork SynchronizerWith JED204B/JED204C and BAW VCO for Wireless Communications datasheet | PDF | HTML | 2023年 12月 6日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 引腳 | 下載 |
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VQFN (RGC) | 64 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。