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LP2998

現行

具關閉接腳的 1.5-A DDR 終端穩壓器

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產品規格表

LP2998

現行
產品規格表 立即訂購

產品詳細資料

Vin (min) (V) 1.35 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Iq (typ) (mA) 0.32 Rating Catalog Operating temperature range (°C) -40 to 125 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L
Vin (min) (V) 1.35 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Iq (typ) (mA) 0.32 Rating Catalog Operating temperature range (°C) -40 to 125 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L
HSOIC (DDA) 8 29.4 mm² 4.9 x 6 SOIC (D) 8 29.4 mm² 4.9 x 6
  • AEC-Q100 Test Guidance with the following results
    (SO PowerPAD-8):
    • Device HBM ESD Classification Level H1C
    • Junction Temperature Range –40°C to 125°C
  • 1.35 V Minimum VDDQ
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • AEC-Q100 Test Guidance with the following results
    (SO PowerPAD-8):
    • Device HBM ESD Classification Level H1C
    • Junction Temperature Range –40°C to 125°C
  • 1.35 V Minimum VDDQ
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown

The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.
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類型 標題 日期
* Data sheet LP2998/LP2998-Q1 DDR Termination Regulator datasheet (Rev. K) PDF | HTML 2014年 8月 20日
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020年 7月 9日
Application note Limiting DDR Termination Regulators’ Inrush Current 2016年 8月 23日
EVM User's guide AN-1813 LP2998 Evaluation Board (Rev. A) 2013年 5月 7日
Application note AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) 2013年 5月 6日
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 2010年 4月 28日
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices 2010年 4月 20日
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) 2010年 3月 31日
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 2010年 3月 26日
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs 2010年 3月 26日
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers 2010年 3月 26日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

LP2998EVAL — 適用於 LP2998 的評估板

The LP2998 evaluation board is designed to provide the design Engineer with a fully functional prototype system in which to evaluate the LP2998 in both a static environment and with a complete memory system.

使用指南: PDF
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模擬型號

LP2998 PSPICE Transient Model (Rev. B)

SNVM695B.ZIP (48 KB) - PSpice Model
下載
模擬型號

LP2998 TINA-TI Transient Reference Design

SNVMB49.TSC (599 KB) - TINA-TI Reference Design
下載
模擬型號

LP2998 TINA-TI Transient Spice Model

SNVMB48.ZIP (39 KB) - TINA-TI Spice Model
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模擬型號

LP2998 Unencrypted PSpice Model

SNVMAF5.ZIP (7 KB) - PSpice Model
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參考設計

TIDA-010011 — 用於保護繼電器處理器模組的高效電源供應架構參考設計

This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
Design guide: PDF
電路圖: PDF
參考設計

PMP10600 — Xilinx® Zynq® 7000 系列 (XC7Z015) 電源解決方案 (5W) 參考設計

The PMP10600.1 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA.   This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator.  It also features one LM3880 for power up and power (...)
Test report: PDF
電路圖: PDF
參考設計

PMP10601 — Xilinx® Zynq® 7000 系列 (XC7Z015) 電源解決方案 (8W) 參考設計

The PMP10601 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015)  FPGA.   This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA.  It also (...)
Test report: PDF
電路圖: PDF
參考設計

PMP10613 — Xilinx Zynq 7000 系列 (XC7Z045) 20W 參考設計

The PMP10613 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z045)  FPGA.   This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA.  It (...)
Test report: PDF
電路圖: PDF
參考設計

PMP9766 — 具有主動式電池平衡的超級電容器備用電源供應參考設計

This reference design describes a backup power circuit which addresses instantaneous protection against power interruptions by using a buck-boost converter and two stacked supercapacitors. The implementation is based on a completely integrated TPS63020 buck-boost converter circuit enabling a small (...)
Test report: PDF
電路圖: PDF
參考設計

PMP10630 — Xilinx Kintex UltraScale XCKU040 FPGA 電源解決方案、6W 參考設計

The PMP10630 reference design is a complete high density power solution for Xilinx® Kintex® UltraScale™ XCKU040 FPGA. This design uses an optimal combination of SIMPLE SWITCHER® modules and LDOs to provide all the necessary voltage rails in a small solution size of 36 x 43 mm (1.4 (...)
Test report: PDF
電路圖: PDF
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