SN65DSI84

現行

MIPI® DSI 橋接器至 Flatlink™ LVDS 單通道 DSI 至雙鏈路 LVDS 橋接器

產品詳細資料

Type Bridge Protocols LVDS, MIPI DSI Rating Catalog Speed (max) (Gbpp) 4 Supply voltage (V) 1.8 Operating temperature range (°C) -40 to 85
Type Bridge Protocols LVDS, MIPI DSI Rating Catalog Speed (max) (Gbpp) 4 Supply voltage (V) 1.8 Operating temperature range (°C) -40 to 85
NFBGA (ZXH) 64 25 mm² 5 x 5
  • Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Single channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1 Gbps per lane
  • Supports 18 bpp and 24-bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60-fps WUXGA 1920 × 1200 resolution at 18-bpp and 24-bpp color, 60 fps 1366 × 768 at 18 bpp and 24 bpp
  • FlatLink™ output configurable for single-link or dual-link LVDS
  • Supports single channel DSI to dual-link LVDS operating mode
  • LVDS output clock range of 25 MHz to 154 MHz in dual-link or single-link modes
  • LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
  • 1.8-V main VCC power supply
  • Low power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support
  • LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing
  • ESD rating ±2 kV (HBM)
  • Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)
  • Temperature range: –40°C to 85°C
  • Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Single channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1 Gbps per lane
  • Supports 18 bpp and 24-bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60-fps WUXGA 1920 × 1200 resolution at 18-bpp and 24-bpp color, 60 fps 1366 × 768 at 18 bpp and 24 bpp
  • FlatLink™ output configurable for single-link or dual-link LVDS
  • Supports single channel DSI to dual-link LVDS operating mode
  • LVDS output clock range of 25 MHz to 154 MHz in dual-link or single-link modes
  • LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
  • 1.8-V main VCC power supply
  • Low power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support
  • LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing
  • ESD rating ±2 kV (HBM)
  • Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)
  • Temperature range: –40°C to 85°C

The SN65DSI84 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS interface with four data lanes per link.

The SN65DSI84 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry compliant interface technology, the SN65DSI84 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.

The SN65DSI84 is implemented in a small outline 5x5mm nFBGA at 0.5 mm pitch package, and operates across a temperature range from -40°C to 85°C.

The SN65DSI84 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS interface with four data lanes per link.

The SN65DSI84 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry compliant interface technology, the SN65DSI84 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.

The SN65DSI84 is implemented in a small outline 5x5mm nFBGA at 0.5 mm pitch package, and operates across a temperature range from -40°C to 85°C.

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類型 標題 日期
* Data sheet MIPI DSI Bridge to Flat Link LVDS Single Channel DSI to Dual-Link LVDS Bridge datasheet (Rev. H) 2020年 11月 11日
Application note Troubleshooting SN65DSI8x - Tips and Tricks 2018年 8月 27日
EVM User's guide SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and Implementation Guide 2015年 11月 17日
Application note SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation Guide (Rev. A) 2013年 4月 11日
Application note SN65DSI8x Video Configuration Guide and Configuration Tool Software Users Manual (Rev. B) 2013年 4月 8日

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開發板

SN65DSI85EVM — SN65DSI85 雙通道 MIPI® DSI 轉 Dual-Link FlatLink™ LVDS 橋接評估模組

The SN65DSI85EVM evaluation module (EVM) is a printed circuit board (PCB) that helps customers implementthe SN65DSI85 device in system hardware. This EVM can be used as a hardware reference design for any implementation using the SN65DSI85 device. The SN65DSI85EVM includes (...)
使用指南: PDF
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IDE、配置、編譯器或偵錯程式

DSI-TUNER — 調諧器視訊配置軟體工具

DSI 調諧器視訊配置工具可產生使用 SN65DSI8x DSI 轉 LVDS 橋接裝置,傳輸 DSI 資料至 LVDS 面板所需的視訊計時和配置暫存器值。計時和暫存器值是根據工具中提供的輸入欄位中輸入的值來計算。
模擬型號

SN65DSI84 IBIS Model

SLLM203.ZIP (254 KB) - IBIS Model
模擬型號

SN65DSI85 Hspice Model

SLLJ007.ZIP (1092 KB) - HSpice Model
模擬工具

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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NFBGA (ZXH) 64 Ultra Librarian

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