SN74ACT7803

Name: SN74ACT7803
Brand: TI
SKU: SN74ACT7803
Price: 18.043 USD

現行

512 x 18 同步 FIFO 記憶體

立即訂購

產品規格表

document-pdfAcrobat 512 X 18 Clocked First-In, First-Out Memory datasheet (Rev. C) (英文)

SN74ACT7803

現行

產品規格表

立即訂購

產品詳細資料

Technology family

ACT

Rating

Military

Operating temperature range (°C)

0 to 70

Technology family

ACT

Rating

Military

Operating temperature range (°C)

0 to 70

SSOP (DL)

56

190.647 mm² 18.42 x 10.35

Member of the Texas Instruments Widebus^TM Family
Free-Running Read and Write Clocks Can Be Asynchronous or Coincident
Read and Write Operations Synchronized to Independent System Clocks
Input-Ready Flag Synchronized to Write Clock
Output-Ready Flag Synchronized to Read Clock
512 Words by 18 Bits
Low-Power Advanced CMOS Technology
Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag
Bidirectional Configuration and Width Expansion Without Additional Logic
Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
Data Rates up to 67 MHz
Pin-to-Pin Compatible With SN74ACT7805 and SN74ACT7813
Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing
Widebus and OEC are trademarks of Texas Instruments Incorporated.

Member of the Texas Instruments Widebus^TM Family
Free-Running Read and Write Clocks Can Be Asynchronous or Coincident
Read and Write Operations Synchronized to Independent System Clocks
Input-Ready Flag Synchronized to Write Clock
Output-Ready Flag Synchronized to Read Clock
512 Words by 18 Bits
Low-Power Advanced CMOS Technology
Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag
Bidirectional Configuration and Width Expansion Without Additional Logic
Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
Data Rates up to 67 MHz
Pin-to-Pin Compatible With SN74ACT7805 and SN74ACT7813
Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing
Widebus and OEC are trademarks of Texas Instruments Incorporated.

The SN74ACT7803 is a 512-word × 18-bit FIFO suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed V_CC and GND pins, along with Texas Instruments patented output edge control (OEC^TM) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.

The SN74ACT7803 is characterized for operation from 0°C to 70°C.

The SN74ACT7803 is a 512-word × 18-bit FIFO suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed V_CC and GND pins, along with Texas Instruments patented output edge control (OEC^TM) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.

The SN74ACT7803 is characterized for operation from 0°C to 70°C.

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檢視所有 14

	類型	標題	日期
*	Data sheet	512 X 18 Clocked First-In, First-Out Memory datasheet (Rev. C)	1998年 4月 1日
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	2021年 7月 26日
	Selection guide	Logic Guide (Rev. AB)	2017年 6月 12日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	2015年 12月 2日
	User guide	LOGIC Pocket Data Book (Rev. B)	2007年 1月 16日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	2004年 7月 8日
	Application note	Selecting the Right Level Translation Solution (Rev. A)	2004年 6月 22日
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	2002年 8月 29日
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	1997年 6月 1日
	Application note	Designing With Logic (Rev. C)	1997年 6月 1日
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc	1996年 4月 1日
	Application note	FIFO Memories: Solutions For Increasing Clock Rates And Data Widths (Rev. A)	1996年 3月 1日
	Application note	Power-Dissipation Calculations for TI FIFO Products (Rev. A)	1996年 3月 1日
	Application note	Simultaneous-Switching Noise Analysis For Texas Instruments FIFO Products (Rev. A)	1996年 3月 1日

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SN74ACT7803

512 x 18 同步 FIFO 記憶體

SN74ACT7803

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