SN74ACT7806

Name: SN74ACT7806
Brand: TI
SKU: SN74ACT7806
Price: 14.837 USD

現行

256 x 18 非同步 FIFO 記憶體

立即訂購

產品規格表

document-pdfAcrobat 256 X 18 Strobed First-In, First-Out Memory datasheet (Rev. C) (英文)

SN74ACT7806

現行

產品規格表

立即訂購

產品詳細資料

Technology family

ACT

Rating

Military

Operating temperature range (°C)

0 to 70

Technology family

ACT

Rating

Military

Operating temperature range (°C)

0 to 70

SSOP (DL)

56

190.647 mm² 18.42 x 10.35

Member of the Texas Instruments Widebus^TM Family
Load Clock and Unload Clock Can Be Asynchronous or Coincident
256 Words by 18 Bits
Low-Power Advanced CMOS Technology
Full, Empty, and Half-Full Flags
Programmable Almost-Full/Almost-Empty Flag
Fast Access Times of 15 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
Data Rates up to 50 MHz
3-State Outputs
Pin-to-Pin Compatible With SN74ACT7804 and SN74ACT7814
Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing
Widebus is a trademark of Texas Instruments Incorporated.

Member of the Texas Instruments Widebus^TM Family
Load Clock and Unload Clock Can Be Asynchronous or Coincident
256 Words by 18 Bits
Low-Power Advanced CMOS Technology
Full, Empty, and Half-Full Flags
Programmable Almost-Full/Almost-Empty Flag
Fast Access Times of 15 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
Data Rates up to 50 MHz
3-State Outputs
Pin-to-Pin Compatible With SN74ACT7804 and SN74ACT7814
Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing
Widebus is a trademark of Texas Instruments Incorporated.

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT7806 is a 256-word by 18-bit FIFO for high speed and fast access times. It processes data at rates up to 50 MHz and access times of 15 ns in a bit-parallel format.

Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK) input. The memory is full when the number of words clocked in exceeds the number of words clocked out by 256. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect.

Status of the FIFO memory is monitored by the full (FULL\), empty (EMPTY\), half-full (HF), and almost-full/almost-empty (AF/AE) flags. The FULL\ output is low when the memory is full and high when the memory is not full. The EMPTY\ output is low when the memory is empty and high when it is not empty. The HF output is high when the FIFO contains 128 or more words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN\) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (256 - Y) or more words. The AF/AE flag is low when the FIFO contains between (X + 1) and (255 - Y) words.

A low level on the reset (RESET\) input resets the internal stack pointers and sets FULL\ high, HF low, and EMPTY\ low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up.The first word loaded into empty memory causes EMPTY\ to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. The data outputs are noninverting with respect to the data inputs and are in the high-impedance state when the output-enable (OE\) input is high.

The SN74ACT7806 is characterized for operation from 0°C to 70°C.

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT7806 is a 256-word by 18-bit FIFO for high speed and fast access times. It processes data at rates up to 50 MHz and access times of 15 ns in a bit-parallel format.

Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK) input. The memory is full when the number of words clocked in exceeds the number of words clocked out by 256. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect.

Status of the FIFO memory is monitored by the full (FULL\), empty (EMPTY\), half-full (HF), and almost-full/almost-empty (AF/AE) flags. The FULL\ output is low when the memory is full and high when the memory is not full. The EMPTY\ output is low when the memory is empty and high when it is not empty. The HF output is high when the FIFO contains 128 or more words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN\) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (256 - Y) or more words. The AF/AE flag is low when the FIFO contains between (X + 1) and (255 - Y) words.

A low level on the reset (RESET\) input resets the internal stack pointers and sets FULL\ high, HF low, and EMPTY\ low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up.The first word loaded into empty memory causes EMPTY\ to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. The data outputs are noninverting with respect to the data inputs and are in the high-impedance state when the output-enable (OE\) input is high.

The SN74ACT7806 is characterized for operation from 0°C to 70°C.

open-in-new

尋找其它專業邏輯 IC

下載觀看有字幕稿的影片影片

技術文件

star

=TI 所選的此產品重要文件

找不到結果。請清除您的搜尋條件，然後再試一次。

檢視所有 13

	類型	標題	日期
*	Data sheet	256 X 18 Strobed First-In, First-Out Memory datasheet (Rev. C)	1998年 4月 1日
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	2021年 7月 26日
	Selection guide	Logic Guide (Rev. AB)	2017年 6月 12日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	2015年 12月 2日
	User guide	LOGIC Pocket Data Book (Rev. B)	2007年 1月 16日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	2004年 7月 8日
	Application note	Selecting the Right Level Translation Solution (Rev. A)	2004年 6月 22日
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	2002年 8月 29日
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	1997年 6月 1日
	Application note	Designing With Logic (Rev. C)	1997年 6月 1日
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc	1996年 4月 1日
	Application note	FIFO Memories: Solutions For Increasing Clock Rates And Data Widths (Rev. A)	1996年 3月 1日
	Application note	Power-Dissipation Calculations for TI FIFO Products (Rev. A)	1996年 3月 1日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

封裝	引腳	下載
SSOP (DL)	56	檢視選項

適用 TI 的評估品項標準條款與條件。

SN74ACT7806

256 x 18 非同步 FIFO 記憶體

SN74ACT7806

產品詳細資料

技術文件

設計與開發

訂購與品質

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

影片系列

影片