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邏輯和電壓轉換
電壓轉換器及電平移位器
固定方向電壓轉換器

SN74LV4T125

現行

具三態輸出 CMOS 邏輯位準移位器的單電源四緩衝器閘

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產品規格表

SN74LV4T125

現行
產品規格表 立即訂購

產品詳細資料

Technology family LV-A Applications SPI Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 19 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -16 IOL (max) (mA) -16 Supply current (max) (µA) 5.5 Features 12.25, 32 Input type TTL-Compatible CMOS Output type 3-State, Balanced CMOS Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-A Applications SPI Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 19 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -16 IOL (max) (mA) -16 Supply current (max) (µA) 5.5 Features 12.25, 32 Input type TTL-Compatible CMOS Output type 3-State, Balanced CMOS Rating Catalog Operating temperature range (°C) -40 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5
  • Single-Supply Voltage Translator at 5.0-V, 3.3-V, 2.5-V, and 1.8-V VCC
  • Operating Range of 1.8 V to 5.5 V
  • Up Translation
    • 1.2 V(1) to 1.8 V at 1.8-V VCC
    • 1.5 V(1) to 2.5 V at 2.5-V VCC
    • 1.8 V(1) to 3.3 V at 3.3-V VCC
    • 3.3 V to 5.0 V at 5.0-V VCC
  • Down Translation
    • 3.3 V to 1.8 V at 1.8-V VCC
    • 3.3 V to 2.5 V at 2.5-V VCC
    • 5.0 V to 3.3 V at 3.3-V VCC
  • Logic Output is Referenced to VCC
  • Characterized up to 50 MHz at 3.3-V VCC
  • 5.5 V Tolerance on Input Pins
  • –40°C to 125°C Operating Temperature Range
  • Pb-Free Packages Available: SC-70 (RGY)
    • 3.5 × 3.5 × 1 mm
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Supports Standard Logic Pinouts
  • Ioff Support Partial-Power-Down Mode Operation
  • CMOS Output B Compatible with AUP125, LVC125 (1)

(1)Refer the VIH/VIL and output drive for lower VCC condition.
  • Single-Supply Voltage Translator at 5.0-V, 3.3-V, 2.5-V, and 1.8-V VCC
  • Operating Range of 1.8 V to 5.5 V
  • Up Translation
    • 1.2 V(1) to 1.8 V at 1.8-V VCC
    • 1.5 V(1) to 2.5 V at 2.5-V VCC
    • 1.8 V(1) to 3.3 V at 3.3-V VCC
    • 3.3 V to 5.0 V at 5.0-V VCC
  • Down Translation
    • 3.3 V to 1.8 V at 1.8-V VCC
    • 3.3 V to 2.5 V at 2.5-V VCC
    • 5.0 V to 3.3 V at 3.3-V VCC
  • Logic Output is Referenced to VCC
  • Characterized up to 50 MHz at 3.3-V VCC
  • 5.5 V Tolerance on Input Pins
  • –40°C to 125°C Operating Temperature Range
  • Pb-Free Packages Available: SC-70 (RGY)
    • 3.5 × 3.5 × 1 mm
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Supports Standard Logic Pinouts
  • Ioff Support Partial-Power-Down Mode Operation
  • CMOS Output B Compatible with AUP125, LVC125 (1)

(1)Refer the VIH/VIL and output drive for lower VCC condition.

SN74LV4T125 is a low-voltage CMOS buffer gate that operates at a wider voltage range for portable, telecom, industrial, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to match 1.8-V input logic at VCC = 3.3 V and can be used in 1.8 V to 3.3 V level-up translation. In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output at VCC = 2.5 V). The wide VCC range of 1.8 V to 5.5 V allows the generation of desired output levels to connect to controllers or processors.

The SN74LV4T125 device is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

SN74LV4T125 is a low-voltage CMOS buffer gate that operates at a wider voltage range for portable, telecom, industrial, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to match 1.8-V input logic at VCC = 3.3 V and can be used in 1.8 V to 3.3 V level-up translation. In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output at VCC = 2.5 V). The wide VCC range of 1.8 V to 5.5 V allows the generation of desired output levels to connect to controllers or processors.

The SN74LV4T125 device is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
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類型 標題 日期
* Data sheet SN74LV4T125 Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter datasheet (Rev. C) PDF | HTML 2022年 6月 14日
Application brief Enabling Modular PLC System Designs with Single-Supply Level Translation PDF | HTML 2024年 4月 16日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日

設計與開發

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開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
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開發板

14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組

14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM)，設計用途可支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。

使用指南: PDF | HTML
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模擬型號

SN74LV4T125 IBIS Model

SCLM112.ZIP (50 KB) - IBIS Model
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參考設計

TIDA-01373 — EEPROM 編程工具參考設計

The TIDA-01373 is a reference hardware and software example of a scalable programming tool for the DRV10983, DRV10975, DRV10983-Q1, and DRV10987 integrated BLDC motor drivers. These devices feature configurable EEPROM registers that need to be set to motor-specific parameters. This reference (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01370 — 帶有用於失速偵測的編碼器的閉合迴路步進馬達參考設計

This reference design is used for the stall-detection in a stepper motor driven by DRV8880 in the presence of a closed-loop feedback obtained with an optical rotary incremental encoder.  The reference design shows how to detect a stall using a closed-loop algorithm.
Design guide: PDF
電路圖: PDF
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VQFN (RGY) 14 檢視選項
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