Powerful 16-Bit TMS320C5x CPU
20-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 5-V Operation
25-, 40-, and 50-ns Single-Cycle Instruction Execution Time for 3-V Operation
Single-Cycle 16 × 16-Bit Multiply/Add
224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global)
2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access On-Chip Program ROM
1K, 3K, 6K, 9K × 16-Bit Single-Access On-Chip Program/ Data RAM (SARAM)
1K Dual-Access On-Chip Program/ Data RAM (DARAM)
Full-Duplex Synchronous Serial Port for Coder/Decoder Interface
Time-Division-Multiplexed (TDM) Serial Port
Hardware or Software Wait-State Generation Capability
On-Chip Timer for Control Operations
Repeat Instructions for Efficient Use of Program Space
Buffered Serial Port
Host Port Interface
Multiple Phase-Locked Loop (PLL) Clocking Options (×1, ×2, ×3, ×4, ×5, ×9 Depending on Device)
Block Moves for Data/Program Management
On-Chip Scan-Based Emulation Logic
Boundary Scan
Five Packaging Options
- 100-Pin Quad Flat Package (PJ Suffix)
- 100-Pin Thin Quad Flat Package (PZ Suffix)
- 128-Pin Thin Quad Flat Package (PBK Suffix)
- 132-Pin Quad Flat Package (PQ Suffix)
- 144-Pin Thin Quad Flat Package (PGE Suffix)
Low Power Dissipation and Power-Down Modes:
- 47 mA (2.35 mA/ MIP) at 5 V, 40-MHz Clock (Average)
- 23 mA (1.15 mA/ MIP) at 3 V, 40-MHz Clock (Average)
- 10 mA at 5 V, 40-MHz Clock (IDLE1 Mode)
- 3 mA at 5 V, 40-MHz Clock (IDLE2 Mode)
- 5 mA at 5 V, Clocks Off (IDLE2 Mode)
High-Performance Static CMOS Technology
IEEE Standard 1149.1 Test-Access Port (JTAG)

TI is a trademark of Texas Instruments Incorporated.
IEEE Standard 1149.1\x961990, IEEE Standard Test-Access Port and Boundary-Scan Architecture.
References to 'C5x in this document include both TMS320C5x and TMS320LC5x devices unless specified otherwise.

Powerful 16-Bit TMS320C5x CPU
20-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 5-V Operation
25-, 40-, and 50-ns Single-Cycle Instruction Execution Time for 3-V Operation
Single-Cycle 16 × 16-Bit Multiply/Add
224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global)
2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access On-Chip Program ROM
1K, 3K, 6K, 9K × 16-Bit Single-Access On-Chip Program/ Data RAM (SARAM)
1K Dual-Access On-Chip Program/ Data RAM (DARAM)
Full-Duplex Synchronous Serial Port for Coder/Decoder Interface
Time-Division-Multiplexed (TDM) Serial Port
Hardware or Software Wait-State Generation Capability
On-Chip Timer for Control Operations
Repeat Instructions for Efficient Use of Program Space
Buffered Serial Port
Host Port Interface
Multiple Phase-Locked Loop (PLL) Clocking Options (×1, ×2, ×3, ×4, ×5, ×9 Depending on Device)
Block Moves for Data/Program Management
On-Chip Scan-Based Emulation Logic
Boundary Scan
Five Packaging Options
- 100-Pin Quad Flat Package (PJ Suffix)
- 100-Pin Thin Quad Flat Package (PZ Suffix)
- 128-Pin Thin Quad Flat Package (PBK Suffix)
- 132-Pin Quad Flat Package (PQ Suffix)
- 144-Pin Thin Quad Flat Package (PGE Suffix)
Low Power Dissipation and Power-Down Modes:
- 47 mA (2.35 mA/ MIP) at 5 V, 40-MHz Clock (Average)
- 23 mA (1.15 mA/ MIP) at 3 V, 40-MHz Clock (Average)
- 10 mA at 5 V, 40-MHz Clock (IDLE1 Mode)
- 3 mA at 5 V, 40-MHz Clock (IDLE2 Mode)
- 5 mA at 5 V, Clocks Off (IDLE2 Mode)
High-Performance Static CMOS Technology
IEEE Standard 1149.1 Test-Access Port (JTAG)

TI is a trademark of Texas Instruments Incorporated.
IEEE Standard 1149.1\x961990, IEEE Standard Test-Access Port and Boundary-Scan Architecture.
References to 'C5x in this document include both TMS320C5x and TMS320LC5x devices unless specified otherwise.

The TMS320C5x generation of the Texas Instruments (TI™) TMS320 digital signal processors (DSPs) is fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the 'C5x devices. They execute up to 50 million instructions per second (MIPS).

The 'C5x devices offer these advantages:

Enhanced TMS320 architectural design for increased performance and versatility

Modular architectural design for fast development of spin-off devices

Advanced integrated-circuit processing technology for increased performance

Upward-compatible source code (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.)

Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation

New static-design techniques for minimizing power consumption and maximizing radiation tolerance

Table 1 provides a comparison of the devices in the 'C5x generation. It shows the capacity of on-chip RAM and ROM memories, number of serial and parallel I/O ports, execution time of one machine cycle, and type of package with total pin count.

The TMS320C5x generation of the Texas Instruments (TI™) TMS320 digital signal processors (DSPs) is fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the 'C5x devices. They execute up to 50 million instructions per second (MIPS).

The 'C5x devices offer these advantages:

Enhanced TMS320 architectural design for increased performance and versatility

Modular architectural design for fast development of spin-off devices

Advanced integrated-circuit processing technology for increased performance

Upward-compatible source code (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.)

Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation

New static-design techniques for minimizing power consumption and maximizing radiation tolerance

Table 1 provides a comparison of the devices in the 'C5x generation. It shows the capacity of on-chip RAM and ROM memories, number of serial and parallel I/O ports, execution time of one machine cycle, and type of package with total pin count.

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	類型	標題	日期
*	Data sheet	Digital Signal Processors datasheet (Rev. A)	1996年 4月 1日
	User guide	TMS320C5x Evaluation Module Installation Guide (Rev. C)	1996年 9月 1日
	Application note	Improving 32-Channel DTMF Decoders in PBX Systems Using the TMS320C5x DSP	1996年 6月 1日
	User guide	TMS320C5x DSP Starter Kit User's Guide (Rev. A)	1996年 6月 1日
	Application note	Use of the TMS320C5x Internal Oscillator With External Crystals or Resonators	1995年 7月 1日
	Application note	A PCMCIA TMS320 DSP MediaCard for Sound and Fax/Modem Applications	1995年 3月 1日
	User guide	TMS320C5x Emulator Installation Guide (Rev. B)	1994年 12月 1日
	Application note	Setting Up TMS320 DSP Interrupts in 'C'	1994年 11月 1日
	Application note	Minimizing Quantization Effects Using the TMS320 DSP Family	1994年 7月 1日
	Application note	Telecommunications Applications With the TMS320C5x	1994年 3月 1日
	User guide	TMS320C5x C Source Debugger User's Guide (Rev. B)	1994年 2月 1日
	Application note	Calculation Of TMS320C5x Power Dissipation	1993年 4月 1日
	User guide	Parallel Debug Mgr Addendum to TMS320C4x & TMS320C5x C Source Debugger UGs	1993年 4月 1日

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