TPSI2072-Q1
- Qualified for automotive applications
- AEC-Q100 grade 1: –40 to 125°C T A
- Integrated avalanche rated MOSFETs
- Designed and qualified for reliability for dielectric withstand testing (Hi-Pot)
- I AVA = 2-mA for 5-s pulses, 1-mA for 60-s pulses
- V HIPOT, 5-s = 4300-V with R series > 1.83-MΩ
- V HIPOT, 5-s = 2850-V with R series > 1.1-MΩ
- 600-V standoff voltage
- R ON = 65-Ω (T J = 25°C)
- I OFF = 1-µA at 500-V (T J = 105°C)
- Designed and qualified for reliability for dielectric withstand testing (Hi-Pot)
- Low primary side supply current
- 5-mA single channel, 9-mA two channel ON state current
- Functional Safety Capable
- Documentation available to aid in ISO 26262 and IEC 61508 system design
- Robust isolation barrier:
- > 26 year projected lifetime at 1000-V RMS / 1500-V DC working voltage
- Isolation rating, V ISO, up to 3750-V RMS / 5300-V DC
- SOIC 11-pin (DWQ) package with wide pins for improved thermal performance
- Creepage and clearance ≥ 8-mm (primary-secondary)
- Creepage and clearance ≥ 3-mm (across switch terminals)
- Safety-related certifications
- (Planned) DIN VDE V 0884-11:2017-01
- (Planned) UL 1577 component recognition program
The TPSI2072-Q1 is a two channel isolated solid state relay designed for high voltage automotive and industrial applications. The TPSI2072-Q1 uses TIs high reliability capacitive isolation technology in combination with internal back-to-back MOSFETs to form a completely integrated solution requiring no secondary side power supply. The TPSI2072-Q1 improves system reliability as TIs capacitive isolation technology does not suffer from mechanical wearout or photo degradation failure modes common in mechanical relay and photo relay components.
The primary side of the device is powered by only 9 mA of input current and incorporates fail-safe EN1 and EN2 pins preventing any possibility of back powering the VDD supply. In most applications, the VDD pin of the device should be connected to a system supply between 4.5 V–20 V and the EN1 and EN2 pins of the device should be driven by a GPIO output with logic HI between 2.1 V–20 V. In other applications, the VDD, EN1, and EN2 pins could be driven together directly from the system supply or from a GPIO output.
Each channel on the secondary side consists of back-to-back MOSFETs with a standoff voltage of +/-600 V from SM to S1 and SM to S2. The TPSI2072-Q1 MOSFETs avalanche robustness and thermally conscious package design allow it to robustly support system level dielectric withstand testing (HiPot) and DC fast charger surge currents of up to 2 mA without requiring any external components.
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技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TPSI2072-Q1 2-Channel 600-V, 50-mA, Automotive Isolated Switch with 2-mA Avalanche Rating for Insulation Monitoring and High Voltage Measurements datasheet | PDF | HTML | 2023年 6月 30日 |
Functional safety information | TPSI2072-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA | 2023年 6月 30日 | ||
EVM User's guide | TPSI2072-Q1 EVM User's Guide | PDF | HTML | 2023年 6月 29日 | |
Certificate | TPSI2072Q1EVM EU Declaration of Conformity (DoC) | 2023年 6月 27日 | ||
Product overview | When to use SSR or Isolated Gate Driver | PDF | HTML | 2022年 8月 4日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 引腳 | 下載 |
---|---|---|
SOIC (DWQ) | 11 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。