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Low-Voltage Differential Signaling (LVDS) Design Notes (Rev. A)

Low-voltage differential signaling (LVDS) is a signaling method used for high-speed transmission of binary data over copper. It is well recognized that the benefits of balanced data transmission begin to outweigh the costs over single-ended techniques when signal transition times approach 10 ns. This represents signaling rates of about 30 Mbps or clock rates of 60 MHz (in single-edge clocking systems) and above.

LVDS, as documented in TIA/EIA-644, can have signal transition time as short as 260 ps turning a printed circuit board trace into a transmission line in a few centimeters. Care must be taken when designing with LVDS circuits, such as the SN65LVDS31 quadruple line driver and SN65LVDS32 quadruple line receiver. This document provides some guidelines for the basic application of LVDS.


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