This reference design showcases an interface implementation for connecting multiple high voltage bipolar input, 8-channel, mux-input SAR ADCs (6) with the Sitara Arm processors for expanding the number of input channels using Programmable Real-time Unit (PRU-ICSS). ADCs are configured for simultaneous sampling of the same channels across all ADCs. The design highlights the capability of PRU-ICSS to handle 1536ksps (each sample = 16 bits) data rate by sampling 640 samples per line cycle. For 50Hz cycle, this corresponds to 32ksps per channel across 6 ADCs simultaneously (640 samples/cycle*50Hz*6 ADCs*8 Ch = 1536ksps). Also, the second PRU is used to post process the data to achieve coherent sampling.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | Flexible Interface (PRU-ICSS) Reference Design for Simultaneous, Coherent DAQ (Rev. A) | Jan. 03, 2019 | |
| Technical article | Improving sensor DAQ performance using the PRU-ICSS for grid protection and contro | PDF | HTML | Oct. 09, 2018 | |
| Technical article | Interfacing multiple ADCs to a single processor for grid protection and control | PDF | HTML | Sep. 13, 2018 | |
| Application note | HSR/PRP Solutions on Sitara Processors for Grid Substation Communication | Apr. 17, 2018 | ||
| Technical article | Analog interfacing for grid infrastructure with Sitara processors | PDF | HTML | Feb. 15, 2018 |
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