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TIPD112 Design File
(ZIP 1882 KB)
12 Jun 2013 31 views
- 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step Response (Rev. C)
(PDF 1796 KB)
02 Feb 2017 78 views
This TI Verified Design is a high performance data acquisition system (DAQ) using an 18-bit SAR ADC, ADS8881 at a throughput of 1MSPS. This design has been optimized to provide 18-bit settling performance for a Full Scale Step Input signal, thus leading to excellent system linearity. Such an input stimulus is more applicable in MUXed applications for transition between channels with different input voltages. The input driver for the ADC uses the OPA350 for high bandwidth (small & large signal), output current drive and linear rail-to-rail input and output operation. The reference buffer drive utilizes a composite buffer made out of THS4281 & OPA333 to get the desired performance at lowest power consumption. This DAQ block achieves a ±2.5LSB INL performance for a total power consumption of less than 70mW.
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- 18 Bit, 1Msps Sampling Rate
- DC, MUX'ed, and Full Scale Step Inputs
- Optimization: Transient Settling
- Power: 70mW @ AVDD = 5V
- Utilizes ADS8881 (18bit, 1Msps SAR ADC), OPA2350 (Input), THS4281 + OPA333 + REF5045 (Reference)