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- Multichannel JESD204B 15-GHz Clocking Reference Design (Rev. A)
(PDF 2105 KB)
14 Jun 2017 1,056 views
- TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C)
(PDF 6670 KB)
11 Jan 2016 1,541 views
- ADCxxDJxx00 Evaluation Module User's Guide (Rev. A)
(PDF 858 KB)
09 Jan 2018 1,735 views
High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 wideband PLL with integrated VCOs to generate a 10 MHz to 15 GHz clock and SYSREF for JESD204B interfaces. The 10 KHz offset phase noise is < -104 dBc/Hz for a 15 GHz clock frequency. By using TI’s ADC12DJ3200 high speed converter EVMs, a board-to-board clock skew of <10ps is achieved and a SNR of 49.6 dB with a 5.25 GHz input signal. All key design theories are described, guiding users through the part selection process and design optimization. Finally, schematic, board layout, hardware testing, and results are also presented.
- Up to 15GHz sample clock generation
- Multi-channel JESD204B compliant clock solution
- Low phase noise clocking for RF sampling ADC/DAC
- Configurable phase synchronization to achieve low skew in multi-channel system
- Supports TI’s high-speed converter and capture cards (ADC12DJ3200EVM, TSW14J56 / TSW14J57)