SLVSEN9A April   2019  – May 2020 ADC12DJ5200RF

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. Features
  2. Applications
  3. Description
    1.     ADC12DJ5200RF Block Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Comparison
      2. 7.3.2  Analog Inputs
        1. 7.3.2.1 Analog Input Protection
        2. 7.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.2.3 Analog Input Offset Adjust
      3. 7.3.3  ADC Core
        1. 7.3.3.1 ADC Theory of Operation
        2. 7.3.3.2 ADC Core Calibration
        3. 7.3.3.3 Analog Reference Voltage
        4. 7.3.3.4 ADC Overrange Detection
        5. 7.3.3.5 Code Error Rate (CER)
      4. 7.3.4  Temperature Monitoring Diode
      5. 7.3.5  Timestamp
      6. 7.3.6  Clocking
        1. 7.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.6.3.2 Automatic SYSREF Calibration
      7. 7.3.7  Programmable FIR Filter (PFIR)
        1. 7.3.7.1 Dual Channel Equalization
        2. 7.3.7.2 Single Channel Equalization
        3. 7.3.7.3 Time Varying Filter
      8. 7.3.8  Digital Down Converters (DDC)
        1. 7.3.8.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.8.1.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.8.1.2 NCO Selection
          3. 7.3.8.1.3 Basic NCO Frequency Setting Mode
          4. 7.3.8.1.4 Rational NCO Frequency Setting Mode
          5. 7.3.8.1.5 NCO Phase Offset Setting
          6. 7.3.8.1.6 NCO Phase Synchronization
        2. 7.3.8.2 Decimation Filters
        3. 7.3.8.3 Output Data Format
        4. 7.3.8.4 Decimation Settings
          1. 7.3.8.4.1 Decimation Factor
          2. 7.3.8.4.2 DDC Gain Boost
      9. 7.3.9  JESD204C Interface
        1. 7.3.9.1 Transport Layer
        2. 7.3.9.2 Scrambler
        3. 7.3.9.3 Link Layer
        4. 7.3.9.4 8B/10B Link Layer
          1. 7.3.9.4.1 Data Encoding (8B/10B)
          2. 7.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.9.4.3 Code Group Synchronization (CGS)
          4. 7.3.9.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.9.4.5 Frame and Multiframe Monitoring
        5. 7.3.9.5 64B/66B Link Layer
          1. 7.3.9.5.1 64B/66B Encoding
          2. 7.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 7.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 7.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 7.3.9.5.3.2 Forward Error Correction (FEC) Mode
          4. 7.3.9.5.4 Initial Lane Alignment
          5. 7.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.9.6 Physical Layer
          1. 7.3.9.6.1 SerDes Pre-Emphasis
        7. 7.3.9.7 JESD204C Enable
        8. 7.3.9.8 Multi-Device Synchronization and Deterministic Latency
        9. 7.3.9.9 Operation in Subclass 0 Systems
      10. 7.3.10 Alarm Monitoring
        1. 7.3.10.1 NCO Upset Detection
        2. 7.3.10.2 Clock Upset Detection
        3. 7.3.10.3 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 7.4.4 JESD204C Modes
        1. 7.4.4.1 JESD204C Transport Layer Data Formats
        2. 7.4.4.2 64B/66B Sync Header Stream Configuration
        3. 7.4.4.3 Dual DDC and Redundant Data Mode
      5. 7.4.5 Power-Down Modes
      6. 7.4.6 Test Modes
        1. 7.4.6.1 Serializer Test-Mode Details
        2. 7.4.6.2 PRBS Test Modes
        3. 7.4.6.3 Clock Pattern Mode
        4. 7.4.6.4 Ramp Test Mode
        5. 7.4.6.5 Short and Long Transport Test Mode
          1. 7.4.6.5.1 Short Transport Test Pattern
          2. 7.4.6.5.2 Long Transport Test Pattern
        6. 7.4.6.6 D21.5 Test Mode
        7. 7.4.6.7 K28.5 Test Mode
        8. 7.4.6.8 Repeated ILA Test Mode
        9. 7.4.6.9 Modified RPAT Test Mode
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 SPI_Register_Map Registers
      1. 7.6.1   CONFIG_A Register (Address = 0x0) [reset = 0x30]
        1. Table 69. CONFIG_A Register Field Descriptions
      2. 7.6.2   DEVICE_CONFIG Register (Address = 0x2) [reset = 0x00]
        1. Table 70. DEVICE_CONFIG Register Field Descriptions
      3. 7.6.3   CHIP_TYPE Register (Address = 0x3) [reset = 0x03]
        1. Table 71. CHIP_TYPE Register Field Descriptions
      4. 7.6.4   CHIP_ID Register (Address = 0x4) [reset = 0x0]
        1. Table 72. CHIP_ID Register Field Descriptions
      5. 7.6.5   VENDOR_ID Register (Address = 0xC) [reset = 0x0]
        1. Table 73. VENDOR_ID Register Field Descriptions
      6. 7.6.6   USR0 Register (Address = 0x10) [reset = 0x00]
        1. Table 74. USR0 Register Field Descriptions
      7. 7.6.7   CLK_CTRL0 Register (Address = 0x29) [reset = 0x00]
        1. Table 75. CLK_CTRL0 Register Field Descriptions
      8. 7.6.8   CLK_CTRL1 Register (Address = 0x2A) [reset = 0x00]
        1. Table 76. CLK_CTRL1 Register Field Descriptions
      9. 7.6.9   SYSREF_POS Register (Address = 0x2C) [reset = 0x0]
        1. Table 77. SYSREF_POS Register Field Descriptions
      10. 7.6.10  FS_RANGE_A Register (Address = 0x30) [reset = 0xA000]
        1. Table 78. FS_RANGE_A Register Field Descriptions
      11. 7.6.11  FS_RANGE_B Register (Address = 0x32) [reset = 0xA000]
        1. Table 79. FS_RANGE_B Register Field Descriptions
      12. 7.6.12  BG_BYPASS Register (Address = 0x38) [reset = 0x00]
        1. Table 80. BG_BYPASS Register Field Descriptions
      13. 7.6.13  TMSTP_CTRL Register (Address = 0x3B) [reset = 0x00]
        1. Table 81. TMSTP_CTRL Register Field Descriptions
      14. 7.6.14  SER_PE Register (Address = 0x48) [reset = 0x00]
        1. Table 82. SER_PE Register Field Descriptions
      15. 7.6.15  INPUT_MUX Register (Address = 0x60) [reset = 0x01]
        1. Table 83. INPUT_MUX Register Field Descriptions
      16. 7.6.16  CAL_EN Register (Address = 0x61) [reset = 0x01]
        1. Table 84. CAL_EN Register Field Descriptions
      17. 7.6.17  CAL_CFG0 Register (Address = 0x62) [reset = 0x01]
        1. Table 85. CAL_CFG0 Register Field Descriptions
      18. 7.6.18  CAL_AVG Register (Address = 0x68) [reset = 0x61]
        1. Table 86. CAL_AVG Register Field Descriptions
      19. 7.6.19  CAL_STATUS Register (Address = 0x6A) [reset = 0x0]
        1. Table 87. CAL_STATUS Register Field Descriptions
      20. 7.6.20  CAL_PIN_CFG Register (Address = 0x6B) [reset = 0x00]
        1. Table 88. CAL_PIN_CFG Register Field Descriptions
      21. 7.6.21  CAL_SOFT_TRIG Register (Address = 0x6C) [reset = 0x01]
        1. Table 89. CAL_SOFT_TRIG Register Field Descriptions
      22. 7.6.22  CAL_LP Register (Address = 0x6E) [reset = 0x88]
        1. Table 90. CAL_LP Register Field Descriptions
      23. 7.6.23  CAL_DATA_EN Register (Address = 0x70) [reset = 0x00]
        1. Table 91. CAL_DATA_EN Register Field Descriptions
      24. 7.6.24  CAL_DATA Register (Address = 0x71) [reset = 0x0]
        1. Table 92. CAL_DATA Register Field Descriptions
      25. 7.6.25  GAIN_TRIM_A Register (Address = 0x7A) [reset = 0x0]
        1. Table 93. GAIN_TRIM_A Register Field Descriptions
      26. 7.6.26  GAIN_TRIM_B Register (Address = 0x7B) [reset = 0x0]
        1. Table 94. GAIN_TRIM_B Register Field Descriptions
      27. 7.6.27  BG_TRIM Register (Address = 0x7C) [reset = 0x0]
        1. Table 95. BG_TRIM Register Field Descriptions
      28. 7.6.28  RTRIM_A Register (Address = 0x7E) [reset = 0x0]
        1. Table 96. RTRIM_A Register Field Descriptions
      29. 7.6.29  RTRIM_B Register (Address = 0x7F) [reset = 0x0]
        1. Table 97. RTRIM_B Register Field Descriptions
      30. 7.6.30  ADC_DITH Register (Address = 0x9D) [reset = 0x0]
        1. Table 98. ADC_DITH Register Field Descriptions
      31. 7.6.31  B0_TIME_0 Register (Address = 0x102) [reset = 0x0]
        1. Table 99. B0_TIME_0 Register Field Descriptions
      32. 7.6.32  B0_TIME_90 Register (Address = 0x103) [reset = 0x0]
        1. Table 100. B0_TIME_90 Register Field Descriptions
      33. 7.6.33  B1_TIME_0 Register (Address = 0x112) [reset = 0x0]
        1. Table 101. B1_TIME_0 Register Field Descriptions
      34. 7.6.34  B1_TIME_90 Register (Address = 0x113) [reset = 0x0]
        1. Table 102. B1_TIME_90 Register Field Descriptions
      35. 7.6.35  B4_TIME_0 Register (Address = 0x142) [reset = 0x0]
        1. Table 103. B4_TIME_0 Register Field Descriptions
      36. 7.6.36  B5_TIME_0 Register (Address = 0x152) [reset = 0x0]
        1. Table 104. B5_TIME_0 Register Field Descriptions
      37. 7.6.37  LSB_CTRL Register (Address = 0x160) [reset = 0x00]
        1. Table 105. LSB_CTRL Register Field Descriptions
      38. 7.6.38  JESD_EN Register (Address = 0x200) [reset = 0x01]
        1. Table 106. JESD_EN Register Field Descriptions
      39. 7.6.39  JMODE Register (Address = 0x201) [reset = 0x02]
        1. Table 107. JMODE Register Field Descriptions
      40. 7.6.40  KM1 Register (Address = 0x202) [reset = 0x1F]
        1. Table 108. KM1 Register Field Descriptions
      41. 7.6.41  JSYNC_N Register (Address = 0x203) [reset = 0x01]
        1. Table 109. JSYNC_N Register Field Descriptions
      42. 7.6.42  JCTRL Register (Address = 0x204) [reset = 0x03]
        1. Table 110. JCTRL Register Field Descriptions
      43. 7.6.43  JTEST Register (Address = 0x205) [reset = 0x00]
        1. Table 111. JTEST Register Field Descriptions
      44. 7.6.44  DID Register (Address = 0x206) [reset = 0x00]
        1. Table 112. DID Register Field Descriptions
      45. 7.6.45  FCHAR Register (Address = 0x207) [reset = 0x00]
        1. Table 113. FCHAR Register Field Descriptions
      46. 7.6.46  JESD_STATUS Register (Address = 0x208) [reset = 0x0]
        1. Table 114. JESD_STATUS Register Field Descriptions
      47. 7.6.47  PD_CH Register (Address = 0x209) [reset = 0x00]
        1. Table 115. PD_CH Register Field Descriptions
      48. 7.6.48  JEXTRA_A Register (Address = 0x20A) [reset = 0x00]
        1. Table 116. JEXTRA_A Register Field Descriptions
      49. 7.6.49  JEXTRA_B Register (Address = 0x20B) [reset = 0x00]
        1. Table 117. JEXTRA_B Register Field Descriptions
      50. 7.6.50  SHMODE Register (Address = 0x20F) [reset = 0x00]
        1. Table 118. SHMODE Register Field Descriptions
      51. 7.6.51  DDC_CFG Register (Address = 0x210) [reset = 0x00]
        1. Table 119. DDC_CFG Register Field Descriptions
      52. 7.6.52  OVR_T0 Register (Address = 0x211) [reset = 0xF2]
        1. Table 120. OVR_T0 Register Field Descriptions
      53. 7.6.53  OVR_T1 Register (Address = 0x212) [reset = 0xAB]
        1. Table 121. OVR_T1 Register Field Descriptions
      54. 7.6.54  OVR_CFG Register (Address = 0x213) [reset = 0x07]
        1. Table 122. OVR_CFG Register Field Descriptions
      55. 7.6.55  CMODE Register (Address = 0x214) [reset = 0x00]
        1. Table 123. CMODE Register Field Descriptions
      56. 7.6.56  CSEL Register (Address = 0x215) [reset = 0x00]
        1. Table 124. CSEL Register Field Descriptions
      57. 7.6.57  DIG_BIND Register (Address = 0x216) [reset = 0x02]
        1. Table 125. DIG_BIND Register Field Descriptions
      58. 7.6.58  NCO_RDIV Register (Address = 0x217) [reset = 0x0000]
        1. Table 126. NCO_RDIV Register Field Descriptions
      59. 7.6.59  NCO_SYNC Register (Address = 0x219) [reset = 0x02]
        1. Table 127. NCO_SYNC Register Field Descriptions
      60. 7.6.60  FREQA0 Register (Address = 0x220) [reset = 0xC0000000]
        1. Table 128. FREQA0 Register Field Descriptions
      61. 7.6.61  PHASEA0 Register (Address = 0x224) [reset = 0x0000]
        1. Table 129. PHASEA0 Register Field Descriptions
      62. 7.6.62  FREQA1 Register (Address = 0x228) [reset = 0xC0000000]
        1. Table 130. FREQA1 Register Field Descriptions
      63. 7.6.63  PHASEA1 Register (Address = 0x22C) [reset = 0x0000]
        1. Table 131. PHASEA1 Register Field Descriptions
      64. 7.6.64  FREQA2 Register (Address = 0x230) [reset = 0xC0000000]
        1. Table 132. FREQA2 Register Field Descriptions
      65. 7.6.65  PHASEA2 Register (Address = 0x234) [reset = 0x0000]
        1. Table 133. PHASEA2 Register Field Descriptions
      66. 7.6.66  FREQA3 Register (Address = 0x238) [reset = 0xC0000000]
        1. Table 134. FREQA3 Register Field Descriptions
      67. 7.6.67  PHASEA3 Register (Address = 0x23C) [reset = 0x0000]
        1. Table 135. PHASEA3 Register Field Descriptions
      68. 7.6.68  FREQB0 Register (Address = 0x240) [reset = 0xC0000000]
        1. Table 136. FREQB0 Register Field Descriptions
      69. 7.6.69  PHASEB0 Register (Address = 0x244) [reset = 0x0000]
        1. Table 137. PHASEB0 Register Field Descriptions
      70. 7.6.70  FREQB1 Register (Address = 0x248) [reset = 0xC0000000]
        1. Table 138. FREQB1 Register Field Descriptions
      71. 7.6.71  PHASEB1 Register (Address = 0x24C) [reset = 0x0000]
        1. Table 139. PHASEB1 Register Field Descriptions
      72. 7.6.72  FREQB2 Register (Address = 0x250) [reset = 0xC0000000]
        1. Table 140. FREQB2 Register Field Descriptions
      73. 7.6.73  PHASEB2 Register (Address = 0x254) [reset = 0x0000]
        1. Table 141. PHASEB2 Register Field Descriptions
      74. 7.6.74  FREQB3 Register (Address = 0x258) [reset = 0xC0000000]
        1. Table 142. FREQB3 Register Field Descriptions
      75. 7.6.75  PHASEB3 Register (Address = 0x25C) [reset = 0x0000]
        1. Table 143. PHASEB3 Register Field Descriptions
      76. 7.6.76  SPIN_ID Register (Address = 0x297) [reset = 0x0]
        1. Table 144. SPIN_ID Register Field Descriptions
      77. 7.6.77  SRC_EN Register (Address = 0x2B0) [reset = 0x00]
        1. Table 145. SRC_EN Register Field Descriptions
      78. 7.6.78  SRC_CFG Register (Address = 0x2B1) [reset = 0x05]
        1. Table 146. SRC_CFG Register Field Descriptions
      79. 7.6.79  SRC_STATUS Register (Address = 0x2B2) [reset = 0x0]
        1. Table 147. SRC_STATUS Register Field Descriptions
      80. 7.6.80  TAD Register (Address = 0x2B5) [reset = 0x00]
        1. Table 148. TAD Register Field Descriptions
      81. 7.6.81  TAD_RAMP Register (Address = 0x2B8) [reset = 0x00]
        1. Table 149. TAD_RAMP Register Field Descriptions
      82. 7.6.82  ALARM Register (Address = 0x2C0) [reset = 0x0]
        1. Table 150. ALARM Register Field Descriptions
      83. 7.6.83  ALM_STATUS Register (Address = 0x2C1) [reset = 0x3F]
        1. Table 151. ALM_STATUS Register Field Descriptions
      84. 7.6.84  ALM_MASK Register (Address = 0x2C2) [reset = 0x3F]
        1. Table 152. ALM_MASK Register Field Descriptions
      85. 7.6.85  FIFO_LANE_ALM Register (Address = 0x2C4) [reset = 0xFFFF]
        1. Table 153. FIFO_LANE_ALM Register Field Descriptions
      86. 7.6.86  TADJ_A Register (Address = 0x310) [reset = 0x0]
        1. Table 154. TADJ_A Register Field Descriptions
      87. 7.6.87  TADJ_B Register (Address = 0x313) [reset = 0x0]
        1. Table 155. TADJ_B Register Field Descriptions
      88. 7.6.88  TADJ_A_FG90_VINA Register (Address = 0x314) [reset = 0x0]
        1. Table 156. TADJ_A_FG90_VINA Register Field Descriptions
      89. 7.6.89  TADJ_B_FG0_VINA Register (Address = 0x315) [reset = 0x0]
        1. Table 157. TADJ_B_FG0_VINA Register Field Descriptions
      90. 7.6.90  TADJ_A_FG90_VINB Register (Address = 0x31A) [reset = 0x0]
        1. Table 158. TADJ_A_FG90_VINB Register Field Descriptions
      91. 7.6.91  TADJ_B_FG0_VINB Register (Address = 0x31B) [reset = 0x0]
        1. Table 159. TADJ_B_FG0_VINB Register Field Descriptions
      92. 7.6.92  OADJ_A_FG0_VINA Register (Address = 0x344) [reset = 0x0]
        1. Table 160. OADJ_A_FG0_VINA Register Field Descriptions
      93. 7.6.93  OADJ_A_FG0_VINB Register (Address = 0x346) [reset = 0x0]
        1. Table 161. OADJ_A_FG0_VINB Register Field Descriptions
      94. 7.6.94  OADJ_A_FG90_VINA Register (Address = 0x348) [reset = 0x0]
        1. Table 162. OADJ_A_FG90_VINA Register Field Descriptions
      95. 7.6.95  OADJ_A_FG90_VINB Register (Address = 0x34A) [reset = 0x0]
        1. Table 163. OADJ_A_FG90_VINB Register Field Descriptions
      96. 7.6.96  OADJ_B_FG0_VINA Register (Address = 0x34C) [reset = 0x0]
        1. Table 164. OADJ_B_FG0_VINA Register Field Descriptions
      97. 7.6.97  OADJ_B_FG0_VINB Register (Address = 0x34E) [reset = 0x0]
        1. Table 165. OADJ_B_FG0_VINB Register Field Descriptions
      98. 7.6.98  GAIN_A0_FGDUAL Register (Address = 0x350) [reset = 0x0]
        1. Table 166. GAIN_A0_FGDUAL Register Field Descriptions
      99. 7.6.99  GAIN_A1_FGDUAL Register (Address = 0x351) [reset = 0x0]
        1. Table 167. GAIN_A1_FGDUAL Register Field Descriptions
      100. 7.6.100 GAIN_B0_FGDUAL Register (Address = 0x352) [reset = 0x0]
        1. Table 168. GAIN_B0_FGDUAL Register Field Descriptions
      101. 7.6.101 GAIN_B1_FGDUAL Register (Address = 0x353) [reset = 0x0]
        1. Table 169. GAIN_B1_FGDUAL Register Field Descriptions
      102. 7.6.102 GAIN_A0_FGDES Register (Address = 0x354) [reset = 0x0]
        1. Table 170. GAIN_A0_FGDES Register Field Descriptions
      103. 7.6.103 GAIN_A1_FGDES Register (Address = 0x355) [reset = 0x0]
        1. Table 171. GAIN_A1_FGDES Register Field Descriptions
      104. 7.6.104 GAIN_B0_FGDES Register (Address = 0x356) [reset = 0x0]
        1. Table 172. GAIN_B0_FGDES Register Field Descriptions
      105. 7.6.105 GAIN_B1_FGDES Register (Address = 0x357) [reset = 0x0]
        1. Table 173. GAIN_B1_FGDES Register Field Descriptions
      106. 7.6.106 PFIR_CFG Register (Address = 0x400) [reset = 0x00]
        1. Table 174. PFIR_CFG Register Field Descriptions
      107. 7.6.107 PFIR_A0 Register (Address = 0x418) [reset = 0x0]
        1. Table 175. PFIR_A0 Register Field Descriptions
      108. 7.6.108 PFIR_A1 Register (Address = 0x41A) [reset = 0x0]
        1. Table 176. PFIR_A1 Register Field Descriptions
      109. 7.6.109 PFIR_A2 Register (Address = 0x41C) [reset = 0x0]
        1. Table 177. PFIR_A2 Register Field Descriptions
      110. 7.6.110 PFIR_A3 Register (Address = 0x41E) [reset = 0x0]
        1. Table 178. PFIR_A3 Register Field Descriptions
      111. 7.6.111 PFIR_A4 Register (Address = 0x420) [reset = 0x0]
        1. Table 179. PFIR_A4 Register Field Descriptions
      112. 7.6.112 PFIR_A5 Register (Address = 0x423) [reset = 0x0]
        1. Table 180. PFIR_A5 Register Field Descriptions
      113. 7.6.113 PFIR_A6 Register (Address = 0x425) [reset = 0x0]
        1. Table 181. PFIR_A6 Register Field Descriptions
      114. 7.6.114 PFIR_A7 Register (Address = 0x427) [reset = 0x0]
        1. Table 182. PFIR_A7 Register Field Descriptions
      115. 7.6.115 PFIR_A8 Register (Address = 0x429) [reset = 0x0]
        1. Table 183. PFIR_A8 Register Field Descriptions
      116. 7.6.116 PFIR_B0 Register (Address = 0x448) [reset = 0x0]
        1. Table 184. PFIR_B0 Register Field Descriptions
      117. 7.6.117 PFIR_B1 Register (Address = 0x44A) [reset = 0x0]
        1. Table 185. PFIR_B1 Register Field Descriptions
      118. 7.6.118 PFIR_B2 Register (Address = 0x44C) [reset = 0x0]
        1. Table 186. PFIR_B2 Register Field Descriptions
      119. 7.6.119 PFIR_B3 Register (Address = 0x44E) [reset = 0x0]
        1. Table 187. PFIR_B3 Register Field Descriptions
      120. 7.6.120 PFIR_B4 Register (Address = 0x450) [reset = 0x0]
        1. Table 188. PFIR_B4 Register Field Descriptions
      121. 7.6.121 PFIR_B5 Register (Address = 0x453) [reset = 0x0]
        1. Table 189. PFIR_B5 Register Field Descriptions
      122. 7.6.122 PFIR_B6 Register (Address = 0x455) [reset = 0x0]
        1. Table 190. PFIR_B6 Register Field Descriptions
      123. 7.6.123 PFIR_B7 Register (Address = 0x457) [reset = 0x0]
        1. Table 191. PFIR_B7 Register Field Descriptions
      124. 7.6.124 PFIR_B8 Register (Address = 0x459) [reset = 0x0]
        1. Table 192. PFIR_B8 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
      2. 8.2.2 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 ADC12DJ5200RF
    3. 8.3 Initialization Set Up
  9. Power Supply Recommendations
    1. 9.1 Power Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • ADC core:
    • 12-bit resolution
    • Up to 10.4 GSPS in single-channel mode
    • Up to 5.2 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20 dBFS, VFS = 1 VPP-DIFF):
      • Dual-channel mode: –151.8 dBFS/Hz
      • Single-channel mode: –154.4 dBFS/Hz
    • ENOB (dual channel, FIN = 2.4 GHz): 8.6 Bits
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8 GHz
    • Usable input frequency range: > 10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16 Gbps
    • Support for 64B, 66B and 8B,10B encoding
    • 8B and10B modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • 4x, 8x, 16x and 32x complex decimation
    • Four independent 32-Bit NCOs per DDC
  • Programmable FIR filter for equalization
  • Power consumption: 4 W
  • Power supplies: 1.1 V, 1.9 V