ADC12DJ5200RF

• ADC core:
  • 12-bit resolution
  • Up to 10.4 GSPS in single-channel mode
  • Up to 5.2 GSPS in dual-channel mode
• Performance specifications:
  • Noise floor (–20 dBFS, V_FS = 1 V_PP-DIFF):
    • Dual-channel mode: –151.8 dBFS/Hz
    • Single-channel mode: –154.4 dBFS/Hz
  • ENOB (dual channel, F_IN = 2.4 GHz): 8.6 Bits
• Buffered analog inputs with V_CMI of 0 V:
  • Analog input bandwidth (–3 dB): 8 GHz
  • Usable input frequency range: > 10 GHz
  • Full-scale input voltage (V_FS, default): 0.8 V_PP
• Noiseless aperture delay (T_AD) adjustment:
  • Precise sampling control: 19-fs Step
  • Simplifies synchronization and interleaving
  • Temperature and voltage invariant delays
• Easy-to-use synchronization features:
  • Automatic SYSREF timing calibration
  • Timestamp for sample marking
• JESD204C serial data interface:
  • Maximum lane rate: 17.16 Gbps
  • Support for 64B, 66B and 8B,10B encoding
  • 8B and10B modes are JESD204B compatible
• Optional digital down-converters (DDC):
  • 4x, 8x, 16x and 32x complex decimation
  • Four independent 32-Bit NCOs per DDC
• Programmable FIR filter for equalization
• Power consumption: 4 W
• Power supplies: 1.1 V, 1.9 V

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The ADC12DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. ADC12DJ5200RF can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. These operating modes allow programmable tradeoffs in channel count and Nyquist bandwidth allows for flexible hardware. Useable input frequency range of up to 10 GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8B/10B and 64B/66B data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay (T_AD) adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.