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ADC12DJ5200RF

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RF-sampling 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS

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RF-sampling 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS

ADC12DJ5200RF

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Product details

Parameters

Sample rate (Max) (MSPS) 5200, 10400 Resolution (Bits) 12 Number of input channels 2, 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 4010 Architecture Folding Interpolating SNR (dB) 56.7 ENOB (Bits) 9 SFDR (dB) 78 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

FCBGA (AAV) 144 — open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • ADC core:
    • 12-bit resolution
    • Up to 10.4 GSPS in single-channel mode
    • Up to 5.2 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20 dBFS, VFS = 1 VPP-DIFF):
      • Dual-channel mode: –151.8 dBFS/Hz
      • Single-channel mode: –154.4 dBFS/Hz
    • ENOB (dual channel, FIN = 2.4 GHz): 8.6 Bits
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8 GHz
    • Usable input frequency range: > 10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16 Gbps
    • Support for 64B, 66B and 8B,10B encoding
    • 8B and10B modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • 4x, 8x, 16x and 32x complex decimation
    • Four independent 32-Bit NCOs per DDC
  • Programmable FIR filter for equalization
  • Power consumption: 4 W
  • Power supplies: 1.1 V, 1.9 V

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open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADC12DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. ADC12DJ5200RF can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. These operating modes allow programmable tradeoffs in channel count and Nyquist bandwidth allows for flexible hardware. Useable input frequency range of up to 10 GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8B/10B and 64B/66B data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.

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Sample availability

Preproduction samples are available (PADC12DJ5200RFAAV). Order now

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 8
Type Title Date
* Datasheet ADC12DJ5200RF 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) May 12, 2020
Application note Impact of PLL Jitter to GSPS ADC's SNR and Performance Optimization Nov. 11, 2020
Technical articles Keys to quick success using high-speed data converters Oct. 13, 2020
Application note Powering Sensitive Noise ADC Designs with the TPS62913 Low-Noise Buck Converter Sep. 30, 2020
Technical articles Step-by-step considerations for designing wide-bandwidth multichannel systems Jun. 04, 2019
Technical articles So, what are S-parameters anyway? May 23, 2019
User guide ADC12DJ5200RF Evaluation Module User's Guide Apr. 05, 2019
Technical articles How to achieve fast frequency hopping Mar. 03, 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
Description

The ADC12DJ5200RF evaluation module (EVM) allows for the evaluation of device ADC12DJ5200RF. The ADC12DJ5200RF is a low-power, 12-bit, dual 5.2-GSPS/single 10.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with programmable NCO (...)

Features
  • Flexible transformer-coupled analog input to allow for a variety of sources and frequencies
  • Easy-to-use software GUI to configure ADC12DJ5200RF, LMX2582, and LMK04828 devices for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through high-speed data converter pro (...)
View details
EVALUATION BOARD Download
Description
This high performance WILD FMC+ DM60 ADC & DAC has two input bandwidth options, internal sample clock options and internal 10MHz reference clock options. The WWDM60 has a choice of speed grades that utilize the ADC12DJ2700, ADC12DJ3200 and ADC12DJ5200RF up to 10GSPS. It allows for ADC and DAC (...)
View details

Software development

FIRMWARE Download
JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP — The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Features
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)
View details

Design tools & simulation

SIMULATION MODEL Download
SLVMCW9.ZIP (37 KB) - IBIS Model
SIMULATION MODEL Download
SLVMD65.ZIP (1533 KB) - IBIS-AMI Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
View details
CALCULATION TOOL Download
RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator
FREQ-DDC-FILTER-CALC — This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of both (...)
Features
  • Frequency planning
  • Analog filtering
  • Decimation filter spur location
View details
DESIGN TOOL Download
SLVRBH0.ZIP (10331 KB)
SCHEMATIC Download
SLVC778.ZIP (16455 KB)

Reference designs

REFERENCE DESIGNS Download
12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer
TIDA-01028 — This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
document-generic Schematic
REFERENCE DESIGNS Download
Scalable 20.8 GSPS reference design for 12 bit digitizers
TIDA-010128 — This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
document-generic Schematic
REFERENCE DESIGNS Download
Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems
TIDA-01027 — This reference design demonstrates an efficient, low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
FCBGA (AAV) 144 View options

Ordering & quality

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