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|*||Data sheet||ADC12DJ5200RF 10.4-GSPS Single Channel or 5.2-GSPS Dual Channel, 12-bit, RF datasheet (Rev. B)||20 Oct 2020|
|User guide||ADCxxDJxx00RF-TRF1208 Evaluation Module||12 Oct 2021|
|Third party documents||JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices||22 Jul 2021|
|User guide||ADCxxDJxx00RF Evaluation Module User's Guide (Rev. A)||28 Jun 2021|
|Analog design journal||Clutter‐free power supplies for RF converters in radar applications (Part 1)||18 Mar 2021|
|Certificate||ADC12DJ5200RFEVM EU Declaration of Conformity (DoC) (Rev. B)||09 Mar 2021|
|Application note||Impact of PLL Jitter to GSPS ADC's SNR and Performance Optimization||11 Nov 2020|
|Technical article||Keys to quick success using high-speed data converters||13 Oct 2020|
|Application note||Powering Sensitive Noise ADC Designs with the TPS62913 Low-Noise Buck Converter||30 Sep 2020|
|Technical article||Step-by-step considerations for designing wide-bandwidth multichannel systems||04 Jun 2019|
|Technical article||So, what are S-parameters anyway?||23 May 2019|
|Technical article||How to achieve fast frequency hopping||03 Mar 2019|
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|FCBGA (AAV)||144||View options|
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