SBAS894A April 2018 – October 2018 ADS112C04
The serial clock (SCL) line is used to clock data in and out of the device. The master always drives the clock line. The ADS112C04 cannot act as a master and as a result can never drive SCL.
The serial data (SDA) line allows for bidirectional communication between the host (the master) and the ADS112C04 (the slave). When the master reads from a ADS112C04, the ADS112C04 drives the data line; when the master writes to a ADS112C04, the master drives the data line.
Data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when the SCL line is low. One clock pulse is generated for each data bit transferred. When in an idle state, the master should hold SCL high.