The ADS114S0x provides an internal bias voltage generator, VBIAS, that can be set to two different levels,
(AVDD + AVSS) / 2 and (AVDD + AVSS) / 12 by using the VB_LEVEL bit in the sensor biasing register (08h). The bias voltage is internally buffered and can be established on the analog inputs AIN0 to AIN5 and AINCOM using the VB_AINx bits in the sensor biasing register (08h). A typical use case for VBIAS is biasing unbiased thermocouples to within the common-mode voltage range of the PGA. A block diagram of the VBIAS voltage generator and connection diagram is shown in Figure 76.
The start-up time of the VBIAS voltage depends on the pin load capacitance. The total capacitance includes any capacitance connected from VBIAS to AVDD, AVSS, and ground. Table 20 lists the VBIAS voltage settling times for various external load capacitances. Ensure the VBIAS voltage is fully settled before starting a conversion.
|LOAD CAPACITANCE||SETTLING TIME|
|0.1 µF||280 µs|
|1 µF||2.8 ms|
|10 µF||28 ms|