The full-scale (gain) calibration word is 16 bits consisting of two 8-bit registers, as shown in the two registers starting with gain calibration register 1. The gain calibration value is straight binary, normalized to a unity-gain correction factor at a register value equal to 4000h. Table 22 shows register values for selected gain factors. Do not exceed the PGA input range limits during gain calibration.
|FSC REGISTER VALUE||GAIN FACTOR|
All gains of the ADS114S0x are factory trimmed to meet the gain error specified in the Electrical Characteristics table at TA = 25°C. When the gain drift of the devices over temperature is very low, there is typically no need for self gain calibration.
The SYGCAL command initiates a system gain calibration, where the user sets the input to full-scale to remove gain error. After the SYGCAL is issued, the FSC register is updated. As with the offset calibration, the CAL_SAMP[1:0] bits determine the number of samples used for a gain calibration.
As with an offset calibration, the device starts a new conversion after a gain calibration and DRDY falls to indicate a new conversion has completed.